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steddyman

Cmod A7 massive GND noise

Question

I have created a circuit to replicate the functionality of an old 8-bit chip that I plan to use the Artix-7 on, and for development I am using a Cmod A7 to prototype.

I have found i am getting a lot of noise on the ground plane of the circuit (around 1.2v P-P).  I have decoupling capacitors around my IC's and a voltage regulator with the correct capacitors.

I thought at first the issue was with something I had missed on my circuit, but if I unplug the Cmod A7 from the DIP48 socket, noise drops to around 200 Mv P-P.

Do I need to do extra work to decouple the Cmod A7 itself?  I can see it has a lot of decoupling capacitors on-board anyway.

Thanks

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@steddyman

Measuring ground noise is not trivial but let's assume that your measurements are correct.

You don't provide a lot of details about your prototype. Are you using a custom PCB with headers for plugging in your CMOD? Are you using a lot of the CMOD IO?

There were a lot of design choices made for the CMODs that aren't optimal for prototyping, which is odd as this is clearly what the modules are intended for. Having a single GND and Vcc pin is one of those choices that are unfortunate. This doesn't make the modules a bad product but might well limit what kinds of things that you can do with them.

Companies that make products that they don't actually use to develop real applications don't always evaluate the correct questions in making design choices.

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yes, some details would help...

Random thought: A possible workaround is to configure unused IO pins as outputs and short them to the ground plane.

In RTL, define as outputs driving zero, set DRIVE to 24 (mA, the maximum value) and SLEW-FAST.

This should provide the minimum-impedance setting for your "software-defined ground pins".

It's a  hack and you may even damage the module if too many "1"s are accidentally driven into short-circuited outputs. Still, taking the risk may be cheaper than the alternatives.

Random thought # 2: Read the data sheet of your capacitors, especially the |Z|(f) curve. There can be massive differences between dedicated RF capacitors to low-ESR to run-of-the-mill capacitor. An FPGA is much more challenging than an 8-bit-era digital chip since its digital transients are so much faster.

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Posted (edited)

Thanks Zygot / xc6lx45

I am using all 48 pins on the Cmod A7, apart from the two analog inputs.  Power to the Cmod A7 is fed directly on pins 24 and 25.  There is a 48 pin DIP socket on my board for the Cmod A7, and 40 pin DIP pins that connect to the original IC location.  Also on my board are a few interface chips such as tri-state buffers and a mux (all SMD and LVC variants).  Pin's 24 and 25 are connected to the 5V and GND pins fed from the 40 pin DIP.  A 3.3V regulator is also used (LMS1585) and is fed from the same pins.  All the rest of the glue logic on my board is fed from this regulator.

I am measuring the GND noise using an Oscilloscope, with one probe on the 8-bit computer ground plane the 40PIN DIP is plugged into and the other on any of the grounds either on my board or the Cmod A7 ground pin.  I see these +1v P-P  variances in the 3.3V outputs of the Cmod A7 and also my IC's too as well as the ground.

The Cmod A7 isn't going to be in my final design, that will be an FPGA directly integrated to the board, but I need to test the viability of it first hence using the Cmod A7 now.

When programming I set all unused outputs to pull-down, but I have also tested with pull-none and not noticed any difference.  The capacitors I am using are 10 uF SMD 0805 ceramic capacitors, but I have also tried soldering on regular tin pot TH 10uF electrolytic capacitors but didn't see any difference.

Edited by steddyman

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Posted (edited)
50 minutes ago, steddyman said:

I am measuring the GND noise using an Oscilloscope, with one probe on the 8-bit computer ground plane the 40PIN DIP is plugged into and the other on any of the grounds either on my board or the Cmod A7 ground pin.

Sometimes this may be ok. Usually, the best approach for many measurements is a good active (FET) differential probe. Sensitive measurements have always, since the days before digital scopes, involved disconnecting those ground clips and using a tip-barrel adapter ( or even a spring type ) approach. It's easy to chase phantoms with most tools, especially oscilloscopes.

50 minutes ago, steddyman said:

I am using all 48 pins on the Cmod A7, apart from the two analog inputs

Likely, this is an issue. Single-ended signals have to have a return path to the source. Not all paths are sufficient. Differential signalling inherently resolves this problem but isn't supported by the CMODs. Perhaps a better platform for your particular project would be a Terasic DE0 Nano. The price is similar but the I/O headers and overall board design might be a better fit. No one rewards me for voicing my opinions and I restrict my commentary to what I know by experience. If you use the Nano (Cyclone IV) you'll want to use Quartus 15. Intel has always made a boatload of money creating artificial pricing tiers by hamstringing their product "families". I'm pretty certain that Quartus is now part of that strategy.

1 hour ago, xc6lx45 said:

A possible workaround is to configure unused IO pins as outputs and short them to the ground plane.

This is better than a random thought. One way to overcome system choice issues, like not providing adequate signal return paths or ground bounce is through this method. Of course, if your design uses every I/O pin then this isn't much of an option; which brings us back to my previous comment that not all platforms are suitable for all projects. To be clear your HDL must assign these pins as driven to ground... and you better be in the habit of checking and re-checking what's in your bitstream before configuring a working FPGA. FPGA development is one area where being a bit 'anal retentive' or perhaps OCD is a benefit (but still a burden)

Edited by zygot

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Thanks for those suggestions.  I am still learning my way with electronics, so I'm trying to fully understand these suggestions.

One critical piece of information I have not included is that I am only operating with a 32 Mhz clock, generated from the 12 Mhz clock on the Cmod A7.  Not exactly leading edge.  Also, the circuit it is interfacing with is expecting no signals faster than 8Mhz.

I do have previous experience of using the Quartus tools and found them much easier to use than the Xilinx ones.  It only took me a couple of days to convert a complex emulation project from one board to the DE2-115.  I now have a DE10-Nano, so I could use that I suppose but I am stubborn to understand why I can't get the Cmod A7 working reliably.  Surely the purpose of selling a device with 40+ IO is based on the assumption that you should be able to use it.

 

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Posted (edited)
48 minutes ago, steddyman said:

I am still learning my way with electronics, so I'm trying to fully understand these suggestions.

Even seasoned EEs sometimes forget their basic training like Kirchoff's Law. (perhaps the CMOD is one example of this ) This is all easier to learn in an environment where there there are co-workers available to smack you upside your head with a few simple but well chosen questions to make you re-think your assumptions when you go astray from reality

 

48 minutes ago, steddyman said:

I do have previous experience of using the Quartus tools and found them much easier to use than the Xilinx ones.

I use both on a regular basis. I started out mostly doing Altera because that's what the companies that I work for used. Only 'mad dogs and Englishmen' , to borrow from an old quote, wants to go through the pain of being competent with more than one set of tools ( I'm included in that set though it's not clear which one best fits...). As of today I find that Quartus is lacking in many of the tool features that I need with respect to Vivado or ISE. For example QUartus simply doesn't have something similar to the Implementation view resources in Vivado or even ISE. And I haven't caught Vivado at hamstringing a device family... so far. One thing about Vivado ( but not ISE ISIM ) is the inability to examine memory contents during simulation. Is this really so hard ?? !!! ???

48 minutes ago, steddyman said:

One critical piece of information I have not included is that I am only operating with a 32 Mhz clock, generated from the 12 Mhz clock on the Cmod A7.  Not exactly leading edge.  Also, the circuit it is interfacing with is expecting no signals faster than 8Mhz.

Don't think that the clock rate is the defining criteria for digital design. I got started in a company where the leading edge was an 8-bit 6800 running at 1 MHz. Even in those days the state of the art low power schottky logic had edge ( slew ) rates that required careful circuit analysis to operate properly. FPGA devices have controllable slew and current outputs... oh, did anyone mention this as a possible way to mitigate your issues? So one analysis is whether your signal path has the bandwidth to accommodate a drivers' requirements; and this is related to slew rate, not clock rate. Another consideration is whether the energy of your signal is absorbed by the receiver or reflects a substantial percentage back and forth on the path between the driver and receiver. And, as I've pointed out is the basics like providing optimal current return flow paths. If you are going to do circuit design you might as well learn the basics....

 

Edited by zygot

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Sounds like I have quite a bit to learn.  Thanks for the detailed response once again.  I wish I did have colleagues to discuss this with, but unfortunately this is my hobby, not my day job.

I've been messing with basic electronics since the days of the Z80 and 6502, but only dipped my toe in and out from time to time.  I went down the development route and have been a software engineer for a long time.  Digital Logic I can understand in my sleep, but actual circuit theory I struggle with.  I wish somebody could provide a simple logical guide to electronics for programmers.

I'll have a search and read up about slew rate and signal reflection.  Thanks

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1 hour ago, steddyman said:

Digital Logic I can understand in my sleep

Here's thee first rule about a digital logic signal. In the real world it doesn't exist. Everything is analog. Sometimes we can pretend that there's such a thing but rarely when designing digital circuits using real components and wires or traces in real circuits.  They don't teach you that in school ( OK so it's been a while... so perhaps things have changed ) but I had to learn this from very early on in my professional career. Even when you view logic in a simplistic 'digital' ( not necessarily binary ) view, for conceptual purposes,  what is the signal state during the time it's changing from one 'logic state' to another? Again, sometimes we can get away with simplistic models but eventually we have to accept real circuits for what they are; and they are analog for almost every necessary analysis.

A similar concept is that of resistance as opposed to impedance. We can get away with simplistic models when currents are low and voltages are low and static but things start getting complicated as soon as any of those are high or alternating.

Keep at it. All you need is curiosity, a bit of motivation, and the interest.

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Thanks a lot for the advice.  Do you have any good recommendations for resources for learning?

I've picked up a heck of a lot already in the last month on this project, and I picked the project I did because I knew it would be a big stretch for me.  I've already learned Verilog including what to do and not do, and a little VHDL.  I've also learned all about pull up and pull down resistors and voltage regulators but I know there is still a long way to go.

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Posted (edited)

I doubt it will fix all the problem but I am fairly certain that 10 µF caps are unsuitable. 100 nF is more like it.

Capacitor impedance is a V-shaped curve over frequency - you want to be on the left half with frequencies of interest (also harmonics, not just the fundamental digital switching rate). Use a capacitor that's too big and you end on the right half, where it goes up, steeply (the capacitor has just become an inductor)

All that said, the CMOD A7 is a great little board but with a single GND pin it does have its limitations. You could have a look at Trenz TE 0726 ... I think I've helped them sell a few of those over the years 🙂 but then it's not nearly as convenient e.g. bring your own JTAG and power.

The "current return path" topic is something you should look into (much easier with a four-layer board).

As a quick hack, note that there are additional ground connectors on the PMOD connector, on the opposite side of the board (which is good).

Edited by xc6lx45

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3 hours ago, steddyman said:

Do you have any good recommendations for resources for learning?

This is a tough one. it wouldn't hurt to start with a basic electrical circuit analysis textbook; but I don't have any recommendations. The ones on my shelves are quite dated and likely not in print. There might be free on-line courses available. It is just good to get an overview of the basics. Back in the day digital logic vendors had some excellent application notes and texts. You could try sneaking around Ti, ON Semi or Microchip ( I think that they own Micrel ). The ECL and PECL vendors had good treatments of transmission line impedance control and termination which is something that I alluded to earlier. 

I did forget to mention that there guidelines for how many IO Bank outputs can switch simultaneously. The Xilinx Series 7 Select IO Reference Guide provides guidance about that. Really, you'll probably find that scanning though whatever available application notes from vendors will, at the least, set on a series of investigative journeys. Vendor these days tend to be less willing to provide really good free knowledge but it's still available; just harder to come by.

The truth is that it's almost impossible to become an expert of a technology by reading; you have to do, fail, figure out why you failed, expand your knowledge and slowly gain insight about stuff that's not formally in writing. This is basically how companies gain knowledge, except that they can afford to hire really well prepared and smart people with a variety of background experiences. I realize that this might sound silly but people with a common interest used to form clubs where they'd gather every month or so to explore, experiment and share information, and work on common project together. Even two people might be able to create a bit of serendipity that one can't.

At this point we've expanded your original query into something quite broad.

 

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Posted (edited)
On 12/31/2019 at 5:28 PM, steddyman said:

I have created a circuit to replicate the functionality of an old 8-bit chip that I plan to use the Artix-7 on, and for development I am using a Cmod A7 to prototype.

Not sure why this came to me after all this thread has gone though but perhaps one more thought might be useful to a few readers.

Digital circuit design and FPGA development are two related, but distinct disciplines. Certainly having experience in the former is instructive to learning and doing the later. One can certainly develop skill at doing FPGA development without doing any digital circuit design. It's less clear, to me at least, how well someone without fairly well developed digital circuit design acumen can evaluate what makes for a good platform choice if the intent is to combine the two. One nice thing about many of the Digilent logic only boards for beginners is the plethora of available interfaces that are available; all requiring no circuit design. One unfortunate thing about Digilent's logic only board offerings is that they all pretty much are intended to be used in the walled PMOD garden. The exception are the the CMODs; but they are all pretty much copies of one design and not everyone is able to evaluate what kinds of project they are great for and what kinds of projects they might not be so great for. So there's the rub. With a CMOD you are out of the garden ( there is the one PMOD to save the day ) and encouraged to combine it with your own circuit creations but that requires a fair amount of knowledge to decide if it's up to the task. Even if you've designed boards with FPGA devices there still might be issues that aren't obvious.

If one is beginning with the later without any experience with the former I suggest trying to put off projects that rely on both. We don't know what exactly the main purpose of the project is for the subject of this thread; or what all of those IO are doing.  To get to my point; it's always a good idea to divide and conquer when doing something that requires multiple disciplines. In the case of an undefined 8-bit processor, having a minimal number of interfaces ( let's go wth a UART ) and concentrating on the HDL side if things might be a first step for a mixed discipline project. That way one can verify the RTL and FPGA flow without having the extra burden  of hardware realities getting in the way. Once that is accomplished expanding the project with custom circuit design interfaces becomes less complicated to debug. Using that PMOD with a known add-on board might be a good second step. At least you can do this within the garden, so to speak.  Following that one might try and expand to using many of the available IO.

We are all tempted to try and do complicated projects in one step. Even companies, who certainly should know better, try and complete a new project requiring multiple areas of expertise that they have yet to master, and in a limited time frame, with limited commitment except to doing it the way that things ave always been done. It's a pretty rare thing when this works out to anyone's satisfaction. Just a thought.

Edited by zygot

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Thanks for all these suggestions.  I've unfortunately managed to blow a tiny zenner diode on the A7 next to the USB connector, so until I can get a replacement and solder it back on I can't really check anything else.  The wife distracted me while I was trying to check the ground noise on the A7 with it removed from my board.  Magic Smoke ensued.

I have the Verilog code working.  I have a logic analyser and oscilloscope tracing the original chip and my replacement and the only differences are the odd blip outside of the regular patterns caused by this noise.  I am fairly confident with my Verilog knowledge.  I understand the concept of defining the hardware function with reference to digital circuit primitives and the differences between combinational and sequential elements, and not treating it like a regular programming language.

xc6lx45, I do use the PMOD connector already in my design for some extra pins that I needed for video output.  I'm however not currently making use of the 3.3V or Ground pins on that connector.  How would I connect those extra ground and 3.3v outputs?  I already have a regulator producing 3.3v, so I can't really connect them to my existing 3.3v regulated output.  Or would I be better abandoning the regulator entirely and driving the rest of my board from the 3.3v outputs on the PMOD connector?

hamster, i'll give that suggestion a go as soon as I have it back up and running.

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I'd consider attaching a wire to the grounds, possibly from the bottom side. I'd leave the 3.3 V alone.

BTW, are you aware of the problem of digital hazards ? Essentially, you are not allowed to drive IO outputs from combinational logic but must register each output. This might be responsible for some of the noise and would cause weird problems when driving edge-sensitive inputs on fast external ICs e.g. a shift register.

You can use an additional higher frequency clock to not introduce more delay / jitter than necessary (say, 200 MHz). Either use the same PLL with a 2nd output at a multiple of the signal frequency, or use a 2nd PLL at arbitrary high frequency and make the the timing to the original clock "don't-care" with a false_path constraint between the clocks e.g.

#set_false_path -from [get_clocks -of_objects [get_nets clk1]] -to [get_clocks -of_objects [get_nets clk2]]
#set_false_path -from [get_clocks -of_objects [get_nets clk2]] -to [get_clocks -of_objects [get_nets clk1]]

 

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Posted (edited)
On 1/2/2020 at 7:00 AM, hamster said:

Clip the oscilloscope ground lead to the probe tip, and wave it near the board..

Tell us what you see...

I've managed to replace the blown zenner and now have the board back up and working.  <moderated>, those components are so tiny!

So, waving the probe above the the circuit (with the ground attached) does produce some noise, but it is a lot less.  The floating image is with the probe with the earth lead attached floating above the board (that was the worst sample).

floating.jpg

The bottom image is measuring the differential between the ground on the main board my cpu emulator is plugged into, and the Cmod A7 earth pin.

direct.jpg

Edited by steddyman

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15 hours ago, xc6lx45 said:

I'd consider attaching a wire to the grounds, possibly from the bottom side. I'd leave the 3.3 V alone.

BTW, are you aware of the problem of digital hazards ? Essentially, you are not allowed to drive IO outputs from combinational logic but must register each output. This might be responsible for some of the noise and would cause weird problems when driving edge-sensitive inputs on fast external ICs e.g. a shift register.

You can use an additional higher frequency clock to not introduce more delay / jitter than necessary (say, 200 MHz). Either use the same PLL with a 2nd output at a multiple of the signal frequency, or use a 2nd PLL at arbitrary high frequency and make the the timing to the original clock "don't-care" with a false_path constraint between the clocks e.g.


#set_false_path -from [get_clocks -of_objects [get_nets clk1]] -to [get_clocks -of_objects [get_nets clk2]]
#set_false_path -from [get_clocks -of_objects [get_nets clk2]] -to [get_clocks -of_objects [get_nets clk1]]

 

Thanks for the continued support.  I did know about digital hazards caused by propagation delay, but I will double check all of my assign statements to signals are being driven from a reg.  It is possible some are not because I've been tweaking how they are assigned to get the signals to change at the right time. I presume it is ok for outputs not to be of type reg so long as they are fed from a reg?

I don't understand the suggestion of having a much higher frequency but unused PLL output.  What does that achieve?

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17 hours ago, steddyman said:

I have the Verilog code working.  I have a logic analyser and oscilloscope tracing the original chip and my replacement and the only differences are the odd blip outside of the regular patterns caused by this noise.

Show us a picture of what you call ground noise; perhaps we are all talking about different things. Show a couple of signal transitions where you suspect there's a problem.

In regular circuit design connections between drivers and receivers need to be treated as transmission lines. If there are impedance mismatches along the way, say a driver with 25 ohm output resistance, a transmission line with 70 ohms resistance, and a receiver termination with 1000 ohms of resistance ( forget about the difference between impedance and resistance for this argument for now ) then there will be reflected energy bouncing back and forth the trace as some energy is absorbed and some reflected everywhere there is a mismatch. The measurable effect of this is over-shoot or under-shoot at either end ( use your scope ) as well as RF noise emission ( sometimes you can be lucky enough to use your radio to hear it ). If it's bad enough this can damage the driver or receiver. If it exceeds the maximum specification or goes more negative than ground then it's likely that you will get data corruption.

You didn't mention yet how you are connecting the CMOD to your target for the micro replacement.

Ground bounce from driving too many outputs simultaneously, impedance mismatches, return current issues, and bulk and noise absorbing power supply capacitor problem are all likely contributors... but don;t assume that this is the entire list of usual suspects.

 

 

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Ok thanks.

I've connected wires from the grounds on the PMOD pins to the bottom of the board.  It hasn't changed the size of the P-P noise on ground, but it has cleared up the signal a lot.  This is a video chip and the VGA output from it is a lot cleaner now than it was before connecting those grounds.

This is how I am connecting in the PMOD to by board.  It is a simple cable looping from the PMOD back to my board with the outputs used as extra bits for driving the VGA signal I am producing.

I will double check I don't have an impedance mismatch by checking the original schematics.  Thanks for the suggestion and continued support.

pmod.jpg

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15 minutes ago, steddyman said:

I will double check I don't have an impedance mismatch by checking the original schematics

Checking the schematics is usually not sufficient to do that analysis. But that last picture is helpful. The extra two ground connections might not be ideal but certainly help with return currents and establishing a common ground reference between the boards.

Since the picture doesn't show it does the 48 pin CMOD footprint really match the micro that it replaces?

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Posted (edited)

No it doesn't.  The original chip is only 40 pins.  I am driving those 40 pins via 74lvc245's.

Edit: I've tried reducing the drive strength on all the pins (apart from the derived clock) from the default of 12 to 4.  It hasn't changed the noise signature or range.

Edited by steddyman

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20 hours ago, steddyman said:

I've tried reducing the drive strength on all the pins (apart from the derived clock) from the default of 12 to 4.  It hasn't changed the noise signature or range.

Have you tried making sure that all of your outputs have slow slew rates?

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6 hours ago, zygot said:

Have you tried making sure that all of your outputs have slow slew rates?

Yes, they are all set to SLOW which is the default.

Thanks

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Posted (edited)

On this topic I've been making an audio DSP board using the CMOD A7, where additional noise is a real pain.

My initial prototype board had some audio noise problems - I couldn't hear it but I could measure it. I initally thought was due to the CMOD-A7 and could not be fixed, but eventually put down to quite a few different causes:

- I had nearly shorted the output of one of the DAC to GND, which as causing spikes on the power rail. Once fixed things were a lot better, but not perfect/

- I had not made any real attempt to stitch the top fill to the ground plain on the bottom - after all it was a hack.

- I didn't have any series resistors in the I2S lines. I added 50 ohm ones (just picked a random value out of the air - might look at this again)

- I had a few capacitor bodges standing up in the air, which could only make things worse

- I was measuring very close to the FPGA, with a high impedance scope probe

So I addressed all of these in the next prototype, and made up a test jig allowing me to measure 30cm from the board and things are much better - to the point I can't reliably measure any additional noise in the audio band.

I guess what I am trying to say is that even with just one GND pin the CMOD-A7 can be part of a low noise audio system, but you have to put some extra thinking and work in to make it happen. 

This may or may not be of use to your use-case.

Edited by hamster

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Thanks hamster

Your's was the only post that I came up with when I googled my problem in the first place.  The audio board sure looks like a cool fpga project.

I also haven't done any work in matching signals on the top to the bottom, in fact some of my bottom ground plain is not contiguous and relies upon via's so join up the ground plan parts.  Not the best idea.

Are the series resistors you have added to slow down the slew rates of the fpga outputs?

 

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