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write and read data with DDR3 SDRAM Arty-7-35T


Question

Hi guys, happy new year!!

I'm currently trying to write and read data from my DDR3 SDRAM block. Instead of using any  IP core, I want to write and read data diractly using Verilog in Vivado. But unforunitely, I can't find the XDC configition in XDC file of my board. so I'm stucking at how t

`timescale 1ns / 1ps
//ram.v
module ram(
    input                   clk_i,
    input                   rst_i,
    input                   wr_en_i,
    input                   rd_en_i,
    input [7:0]             addr_i,
    inout [31:0]            data_io
);

    reg [31:0]          bram[255:0];    
    integer          i;   
    reg [31:0]       data;
//add implementation code here 
    always @(posedge clk_i or posedge rst_i)
    begin
       if (rst_i)   
         begin
           for(i=0;i<=255;i=i+1) //reset
           bram[i] <= 32'b0;
         end
       else if (wr_en_i) begin
            bram[addr_i] <= data_io;
       end
       else if (rd_en_i) begin
            data <= bram[addr_i];
       end
       else begin
        data <= 32'bz;      
       end
    end

    assign data_io = rd_en_i? data : 32'bz;
endmodule

Mater xdc file for arty-35.txto realize my XDC.

The attachment is DDR3 CIRCUIT, XDC file and My verilog code

1577715040(1).jpg

Edited by weilai
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2 answers to this question

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Hi @weilai,

We don't have xdc pins listed out for the DDR3 on the Arty (or our other FPGA boards if memory serves correctly) but instead is handled in a .prj file. The reason for this is because the DDR and the MIG that configures the DDR within Vivado have a lot of different configurations and nuances to consider for it as discussed in your other thread and in this thread. The .prj for the Arty A7 35T is available on the Digilent Github here.

Thanks,
JColvin

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