Zybo Z7 XADC Aux Analog inputs stuck at 0x5999 and 0x5111

[gautam]

Hi there,

I have been not having luck in reading the aux pins on the zybo z7 board. I have setup the system as below:

The XADC is setup with DRP and channel sequencer in continuous mode, with the setup as below:

I can read the voltages on the XADC system monitor dashboard as below:

But the XADC only read 0x5999 on Aux 15 Pin, as seen below:

As you will see above,  Aux 6 and Aux 14 is stuck at 0x5999 and Aux 7 and Aux 15 is fixed at 0x5111.

I don't get any errors only a critical warning:

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

I have been debugging this for two days now and I am unable to fix this issue. So any help to get the analog inputs on aux pins converted is greatly appreciated!

Cheers, Gautam.

[elodg]

I am reading documentation for you at this point: Chapter 3 XADC Register Interface.

"All registers in the register interface are accessible through the dynamic reconfiguration port (DRP). The DRP allows you to access up to 128 16-bit registers (DADDR[6:0]
= 00h to 7Fh). The first 64 access locations (DADDR[6:0] = 00h to 3Fh) are read-only and contain the ADC measurement data. These registers are known as status registers."

[elodg]

VP/VN measures the current consumption of the board, if you add that channel, do you see a voltage that makes sense? Does channel 00h (internal temperature) make sense? Did you tie the aux inputs together and to GND to have at least an expected value for the readings?

There might be a conflict between the JTAG port of the XADC and the DRP you are using in your project. What happens if you move the MODE jumper away from JTAG? You can still program it from SDK.

[gautam]

Hi elodg,

I see that all values are read correctly through the PS directly. When AUX inputs are supplied voltages I see the same values when I read through PS directly in software.

The temperature values are not the same on the DRP interface, it is always around 2degrees higher that the PS read values.

The VP VN is always 0 on DRP, whereas the even AUX input (AUX6, AUX14) registers give 0x5999 and odd AUX input (AUX7,AUX15) registers give 0x5111.

The test were conducted with both mode selection jumper connected to SD card as well as with this jumper completely removed.

I can also see the correct values on the system monitor dashboard in vivado as below (The temperature reading matches with the DRP read values):

The equivalent DRP output is as seen below:

Is there something I am missing? Are there any other test I can perform to troubleshoot this issue?

[elodg]

Checked timing for the drp interface? https://forums.xilinx.com/t5/Other-FPGA-Architecture/7Series-XADC-timing/td-p/368831

[gautam]

I verified that the timing follows as in the ug480 xadc guide.

I am now uncertain about my implementation of DADDR[6:0] address input in xadc wizard block.

 Is there any documentation or explanation on DADDR bus? The xadc guide only says “Address bus for the DRP.”

[elodg]

Ug480 is littered with address definitions for the register map. DADDR is the port that takes this register address.

"All sensors and external analog-input channels have a unique channel address (see Table 3-7, page 45). The measurement result from each channel is stored in a status register with the same address on the DRP."

[gautam]

Yes, I have seen in this 5 bit address for the channel selection. But the xadc_wizard block's DADDR[6:0] input is 7 bit.

What are other two bits used for? Do they select minimum maximum values?

If the other two bits can be ignored, then should the 5 bit address be left (MSB) justified or right (LSB) justified?