So I was wondering for FPGA devices(like the Arty S7), how does one find the maximum time it takes for a primitive to end in a stable state? For example lets say I have an 10 tap FIR filter. In its more simple implementation there are 10 multiplies(which can be done in parallel) and 10 sums(which must be done sequentially although there is a tree based configuration which requires more summers but incurs lower total delay). How do I find the propagation delay for the 10 sums so I can figure out the fastest the FIR filter can process inputs?
Also I'm a little confused on the differences between using VHDL operations(ex: *) verse manually setting up the DSP slices. Will the synthesis tool automatically configure the DSP slices for me if I use the multiply operation? In general how does manually instantiating the primitives compare to using VHDL library oprations?
Question
SigProcbro
Hi,
So I was wondering for FPGA devices(like the Arty S7), how does one find the maximum time it takes for a primitive to end in a stable state? For example lets say I have an 10 tap FIR filter. In its more simple implementation there are 10 multiplies(which can be done in parallel) and 10 sums(which must be done sequentially although there is a tree based configuration which requires more summers but incurs lower total delay). How do I find the propagation delay for the 10 sums so I can figure out the fastest the FIR filter can process inputs?
Also I'm a little confused on the differences between using VHDL operations(ex: *) verse manually setting up the DSP slices. Will the synthesis tool automatically configure the DSP slices for me if I use the multiply operation? In general how does manually instantiating the primitives compare to using VHDL library oprations?
Link to comment
Share on other sites
6 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.