Cmod A7 Vivado: 100MHz-clocking introduction problem by Clocking Wizard

[Takemasa Tamanuki]

Hello there,

I am trying to introduce 100MHz-clocking into RTL-module instead of the 12MHz-sys-clock.

I have made a circuit with connection of [“clk_out1”: Clocking Wizard output] and [pio46: RTL input] (see Fig. 1) and check the pin-out-waveform by the following HDL-statement.

(Here, I chose the pio46 as a clock-route since it is clock-dedicated-pin of ”P_MRCC”.)

---------------

module Clock_testV1( input pio46, output pio1, output pio2 );

reg [0:0] CLK1;   

always @(posedge pio46)   

begin

CLK1 <= CLK1+1'b1;   

end

assign pio1=pio46;

assign pio2=CLK1;

endmodule

--------

However, the pio1 (as well as pio2) output did not show pulsed-waveform (but 3.3V continuous DC output, see Fig. 2. C1: yellow, pio1, C2: blue, pio2)).

On the other hand, If I replace the “pio46” to “sysclk” in my HDL-statement, it works normally corresponding of 12MHz-clock (see Fig. 3. C1(yellow, pio1): 12MHz, C2(blue, pio2): 6MHz).

I would appreciate if you could provide comments to solve (about introduction 100MHz-locking into RTL-module) this issue.

 

PS: I also referred the following sites, but I could not solve my issue.

https://forum.digilentinc.com/topic/5325-vivado-clock_dedicated_route/

https://forum.digilentinc.com/topic/18479-cmod-a7-vivado-2019-cannot-get-past-implementation/

[Takemasa Tamanuki]

Hello again,

My problem which I could not implement 100MHz-clock into RTL module is solved.

I did newly implement the Clocking-wizard from IP-catalog and add (and revise it as appropriate ) a clocking-wizard-template into V-file as following.

----------------

module Clock_testV1(input sysclk, output pio1, output pio2);

reg [0:0] CLK1;

wire reset;

wire clk_out1;

wire locked;

 

always @(posedge clk_out1)   

begin   

CLK1 <= CLK1+1'b1;   

end

 

clk_wiz_0

   (

   .clk_out1(clk_out1),     // output clk_out1

   .reset(reset), // input reset

   .locked(locked),       // output locked

   .clk_in1(sysclk));      // input clk_in1

 

assign pio1=clk_out1;

assign pio2=CLK1;

endmodule

---------------

50MHz (and 25MHz) waveform was confirmed by Analog discovery 2 (Oscilloscope displayed waveform is limited by the band-width of AD2 (30MHz).).

I would appreciate your comments if my clocking-wizard implement procedure is correct.

Fig. 1. Measured waveform (C1(yellow, pio1): 50MHz, C2(blue, pio2): 25MHz).