Question

Hello,

I've been working on a project that I need to use the ip integrator and add an RTL block that I made.

I'm using a Basys 3 board, Vivado 2018.3 and MicroBlaze ip.

I was trying to add the RTL to the source and to the diagram and I used the getting started with ip integrator tutorial.

The tutorial itself worked fine and when I added the RTL It passed the validation, synthesis, implementation and even generating the bitstream but then I couldn't export hardware for programing the MicroBlaze and it gave an error saying "Cannot write hardware definition file as there are no generated IPI blocks".

Correct me if I'm wrong, but I understood that I need to create an ip that contains my RTL project and only then I can add it to the diagram.

If so, does anybody have a tutorial of how to make a new ip? and if that is not the case, what do you think is the problem?

 

thank you,

Netanel.

 

Capture.PNG

Capture2.PNG

Link to post
Share on other sites

3 answers to this question

Recommended Posts

  • 1

Hello @netanel_shor,

Here are some steps that could help you :

1. Open your RTL project that contains the vhdl/verilog files of your RTL module EightPIRSensors.

image.thumb.png.eb98a2eb3c30cd99b537598e21c229db.png

2. Tools -> Create and Package New IP

Untitled.png.d550708a23a176b907c1e2a074e2d372.png

3. Package your current project

image.png.d0511269e37946274592f8bc2081f0e2.png

4. After you choose the location of you IP and hit Next and Finish, it will open up  a window to Package your IP. After you edit the Identification tab, choose the Compatibility, make sure you checked the other tabs too and everything looks alright then you can Package IP.

 

image.thumb.png.4b48911adbd3792af74564714e923d2a.png

5. Add your IP to the block design (make sure that the path of where you saved your Packed IP is added in Settings -> IP -> Repository-> IP Repositories)

image.thumb.png.e1079692d64be85f7dcc40d790f2af55.png

 

Cheers,

Ana-Maria

Edited by Ana-Maria Balas
Link to post
Share on other sites
  • 1

That warning is not critical.

In UG994 Xilinx says:

Quote

ASSOCIATED_BUSIF: The list contains names of bus interfaces, which run at this clock frequency. This parameter takes a colon-separated list (:) of strings as its value. If all interface signals at the boundary do not run at this clock rate, this field is left blank.

If there is a bus interface associated with this clock then you should add this parameter. But I see that you are not using any interfaces. I think is safe to ignore this warning.

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now