adding RTL to ip integrator

[netanel_shor]

Hello,

I've been working on a project that I need to use the ip integrator and add an RTL block that I made.

I'm using a Basys 3 board, Vivado 2018.3 and MicroBlaze ip.

I was trying to add the RTL to the source and to the diagram and I used the getting started with ip integrator tutorial.

The tutorial itself worked fine and when I added the RTL It passed the validation, synthesis, implementation and even generating the bitstream but then I couldn't export hardware for programing the MicroBlaze and it gave an error saying "Cannot write hardware definition file as there are no generated IPI blocks".

Correct me if I'm wrong, but I understood that I need to create an ip that contains my RTL project and only then I can add it to the diagram.

If so, does anybody have a tutorial of how to make a new ip? and if that is not the case, what do you think is the problem?

 

thank you,

Netanel.

 

[Ana-Maria Balas]

Hello @netanel_shor,

Here are some steps that could help you :

1. Open your RTL project that contains the vhdl/verilog files of your RTL module EightPIRSensors.

2. Tools -> Create and Package New IP

3. Package your current project

4. After you choose the location of you IP and hit Next and Finish, it will open up  a window to Package your IP. After you edit the Identification tab, choose the Compatibility, make sure you checked the other tabs too and everything looks alright then you can Package IP.

 

5. Add your IP to the block design (make sure that the path of where you saved your Packed IP is added in Settings -> IP -> Repository-> IP Repositories)

 

Cheers,

Ana-Maria

[netanel_shor]

Hi @Ana-Maria Balas, thank you for the answer.

It looks like this is what I need to continue but, I'm having trouble with the Ports and Interfaces and it gives a warning about a missing parameter for the clk.

Do you know what the problem might be?

 

thanks,

Netanel.

[Ana-Maria Balas]

That warning is not critical.

In UG994 Xilinx says:

Quote

ASSOCIATED_BUSIF: The list contains names of bus interfaces, which run at this clock frequency. This parameter takes a colon-separated list (:) of strings as its value. If all interface signals at the boundary do not run at this clock rate, this field is left blank.

If there is a bus interface associated with this clock then you should add this parameter. But I see that you are not using any interfaces. I think is safe to ignore this warning.