Luigi Posted April 18, 2016 Share Posted April 18, 2016 UCF/XCF data of of SDRAM on board of Genesys 2 isn't inside the provided XDC file (Pin allocation of SDRAM is missing). Anyway Connectivity can be solved manually recovering pin names and functions from the provided board schematic. Should be better to fill these data inside XDC reference file. Link to comment Share on other sites More sharing options...
JColvin Posted April 20, 2016 Share Posted April 20, 2016 Hi Luigi, From my understanding the Genesys 2 doesn't strictly have SDRAM but rather DDR3 instead. But I do agree that it's not listed in the XDC file. I'll ask some of our applications engineers about this to see if they can amend this. Thanks, JColvin Link to comment Share on other sites More sharing options...
jpeyron Posted May 13, 2016 Share Posted May 13, 2016 Hi Luigi, If you are using at least Vivado 2015.1 the board file for the Genesys 2 is available here https://reference.digilentinc.com/vivado/boardfiles2015 the ddr3 has its own constraint file provided in the board files called the mig.prj Here is a link to a forum question that addresses your issue just on a different board. hope this helps you. Thank you, Jon Link to comment Share on other sites More sharing options...
Question
Luigi
UCF/XCF data of of SDRAM on board of Genesys 2 isn't inside the provided XDC file (Pin allocation of SDRAM is missing).
Anyway Connectivity can be solved manually recovering pin names and functions from the provided board schematic.
Should be better to fill these data inside XDC reference file.
Link to comment
Share on other sites
2 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.