JTAG-SMT2-NC JTAG not stable in Vivado or Adept with Xilinx VU9P

[David Allen]

We are using a  JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs?

 

Thanks,

David

[JColvin]

Hi @David Allen,

There should not be any incompatibilities between the JTAG modules and Xilinx Ultrascale+ boards based on previous conversations that I have had with our design engineer. I do know that Adept is not able to program Ultrascale+ boards so you would need to communicate through the Vivado Hardware Manager.

Is this a custom made board or one that already has the JTAG SMT2 NC integrated into it?

Thanks,
JColvin

 

[David Allen]

Hi JColvin,

Depends on how you define custom! The JTAG SMT2 NC is integrated into a daughter card that we use as a solution for front panel JTAG access to two of our dual FPGA carrier boards. These are products our company produces. The daughter cards have worked in the past on all board except these latest two with VU9P FPGAs. Interesting thing is I can never see the chain correctly from Vivado. In Vivado it will always show devices with the wrong device ID. Using Adept or Impact I can scan the chain and see all four devices. Occasionally in Adept it will behave as Vivado does.  Do you have any other tools besides Adept that would help narrow down where the issue may be? Is there a JTAG analyzer available? I've traced the JTAG signals around the board and signal integrity looks OK. I've attached the Vivado and Impact output below. I don't have a screen capture of the Adept output but it does show the correct IDs for the four devices most of the time. I find it interesting that different programs have different results.

 

David

[JColvin]

Hi @David Allen,

I asked one of our design engineers about this and they recommended that you try slowing down the clock frequency of the JTAG scan within Vivado since with the 4 devices in the scan chain, there could be some signal integrity issues due to the added capacitive load depending on how it's routed. They also recalled that Vivado has a default higher clock rate than both Adept and iMPACT so that could be why Vivado is having more difficulty if there are any signal integrity issues.

Let us know how that goes.

Thanks
JColvin

[David Allen]

I've slowed the JTAG clock down to its lowest setting in Vivado and still have the same issue. 

 

David

[JColvin]

Hi @David Allen,

I know you mentioned that Adept was reporting the correct ID codes, but wanted to verify that this is accurate since there is a possibility that Adept would not recognize the Ultrascale chips and just report an incorrect ID code.

Could you let us know what voltage is being applied to VREF and what voltage is being applied to VCCO_0 of the FPGA banks involved in the scan chain?

Thanks,
JColivn

[David Allen]

The Adept chain returns a device ID of 14B31093 with an instruction register length of 18. It shows up as an unknown CPLD but this is the correct ID and IR length (same IDs and IR lengths reported in Vivado when I scan the chain though the PCB header (not through the daughter card)).

 

VCC0_0 is set to 1.8V.

 

VREF on the JTAG SMT2 NC is set to 3.3V.

[David Allen]

We have a 1.8/3.3V level translator between the FPGA and the daughter card with as well.

 

 

[malexander]

@David Allen

What type of device are you plugging into the PCB header when using Vivado? Is it a JTAG-HS3, JTAG-HS3, or something else? I assume you have 3.3V to 1.8V level translators for TMS, TDI, and TCK, and a 1.8V to 3.3V level translator going the opposite direction for TDO. Is this correct?

Thanks,
Michael

[David Allen]

Hi Michael,

Below is a block diagram of the JTAG chain. There are three ways to access it. One on the PCB header, the VPX backplane, and through the daughter card from the ZFMC site. When plugging into the PCB header or backplane header I have used both the JTAG-HS3 and the standard Xilinx programmer. Both work. It is only through the daughter card that we have issues.

[malexander]

@David Allen

Wow that's a lot of multiplexers! I don't see any obvious problem with your diagram. Have you scoped JTAG_REQ_N and VPX_JTAG_EN_N to make sure that they remain stable when the daughter card is being used to access the scan chain? Btw the JTAG-SMT2-NC and JTAG-HS3 use the same USB controller... the software is almost 100 % identical so I very seriously doubt this is software related.

[David Allen]

Sorry for the late reply on this. I was on vacation then other work priorities intervened. I was only able to test JTAG-SMT2-NC with the daughter card and JTAG-HS3 without the daughter card installed. I have checked and JTAG_REQ_N and VPX_JTAG_EN_N are at the correct levels and remain stable while accessing the chain through the daughter card.