ZMOD ADC and DAC with Eclypse board

[Kevin123456]

Just got the Eclypse Z7, seems like a pretty cool board, hoping to build some projects that focus on low latency servos.

Interested in additional information on the Eclypse z7 Syzygy Ports to be used with the Syzygy ADC and DAC.

Could any provide additional information about....

      Any example to get started?

      Calibration with MCU?

       Is there direct access pins to the AD9717 DIN_AWG pins through the Syzgy?

       Syzgy pins out for the ADC and DAC?

Thanks

Kevin

 

From constraint file for Eclypse Z7: 

## Syzygy Port A
#set_property -dict { PACKAGE_PIN N20  } [get_ports { SYZYGY_A_C2P_CLK_N }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
#set_property -dict { PACKAGE_PIN N19  } [get_ports { SYZYGY_A_C2P_CLK_P }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
#set_property -dict { PACKAGE_PIN T17  } [get_ports { SYZYGY_A_D_N[0] }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
#set_property -dict { PACKAGE_PIN T16  } [get_ports { SYZYGY_A_D_P[0] }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
#set_property -dict { PACKAGE_PIN T19  } [get_ports { SYZYGY_A_D_N[1] }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
#set_property -dict { PACKAGE_PIN R19  } [get_ports { SYZYGY_A_D_P[1] }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
#set_property -dict { PACKAGE_PIN T18  } [get_ports { SYZYGY_A_D_N[2] }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
#set_property -dict { PACKAGE_PIN R18  } [get_ports { SYZYGY_A_D_P[2] }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
#set_property -dict { PACKAGE_PIN P18  } [get_ports { SYZYGY_A_D_N[3] }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
#set_property -dict { PACKAGE_PIN P17  } [get_ports { SYZYGY_A_D_P[3] }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
#set_property -dict { PACKAGE_PIN R16  } [get_ports { SYZYGY_A_D_N[4] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
#set_property -dict { PACKAGE_PIN P16  } [get_ports { SYZYGY_A_D_P[4] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
#set_property -dict { PACKAGE_PIN P15  } [get_ports { SYZYGY_A_D_N[5] }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
#set_property -dict { PACKAGE_PIN N15  } [get_ports { SYZYGY_A_D_P[5] }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
#set_property -dict { PACKAGE_PIN K18  } [get_ports { SYZYGY_A_D_N[6] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
#set_property -dict { PACKAGE_PIN J18  } [get_ports { SYZYGY_A_D_P[6] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
#set_property -dict { PACKAGE_PIN K21  } [get_ports { SYZYGY_A_D_N[7] }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
#set_property -dict { PACKAGE_PIN J20  } [get_ports { SYZYGY_A_D_P[7] }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
#set_property -dict { PACKAGE_PIN M20  } [get_ports { SYZYGY_A_P2C_CLK_N }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
#set_property -dict { PACKAGE_PIN M19  } [get_ports { SYZYGY_A_P2C_CLK_P }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
#set_property -dict { PACKAGE_PIN L19  } [get_ports { SYZYGY_A_S[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
#set_property -dict { PACKAGE_PIN K20  } [get_ports { SYZYGY_A_S[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
#set_property -dict { PACKAGE_PIN L18  } [get_ports { SYZYGY_A_S[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
#set_property -dict { PACKAGE_PIN K19  } [get_ports { SYZYGY_A_S[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
#set_property -dict { PACKAGE_PIN L22  } [get_ports { SYZYGY_A_S[20] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
#set_property -dict { PACKAGE_PIN J22  } [get_ports { SYZYGY_A_S[21] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
#set_property -dict { PACKAGE_PIN L21  } [get_ports { SYZYGY_A_S[22] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
#set_property -dict { PACKAGE_PIN J21  } [get_ports { SYZYGY_A_S[23] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
#set_property -dict { PACKAGE_PIN N22  } [get_ports { SYZYGY_A_S[24] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
#set_property -dict { PACKAGE_PIN P22  } [get_ports { SYZYGY_A_S[25] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
#set_property -dict { PACKAGE_PIN M21  } [get_ports { SYZYGY_A_S[26] }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
#set_property -dict { PACKAGE_PIN M22  } [get_ports { SYZYGY_A_S[27] }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]

eclypse-z7-master.xdc

[vicentiu]

Congratulations! You have a sneak peek of a board that is scheduled to release on January 15. A few pieces arrived at distributors early and they mistakenly put them up for sale before the release date.

We’re currently finalizing everything you’re asking about and we’ll have it available for the release.

Did you get just the Eclypse board or do you have the Zmod ADC and DAC also?

[Kevin123456]

Hi Vicentiu,

Yup, got both the ADC and DAC. Really excited to get some designs going.

Cool ill keep an eye open for updates, thanks.

 

[Aenerine]

How comes its scheduled for January 15? Digilent officially announced December 15 2019. I was expecting to be able to purchase the board already.

[vicentiu]

Software development was slower than expected so we pushed it back one month.

[vicentiu]

Hello,

We have the Eclypse Z7 reference and Zmod demo materials posted.

Zmod reference pages:

https://reference.digilentinc.com/reference/zmod/zmodadc/start

https://reference.digilentinc.com/reference/zmod/zmoddac/start

[Jeff K]

Is the 100MS/s ADC reference design the fastest design available?

Are faster designs planned?

[Cristian.Fatu]

Hello,

The maximum sample rate for the chip on ZmodADC1410 (AD9648) is 105 MSPS and the IP is designed for 100MSPS.

This is the only available reference design.

What sample rates do you need?

[ramanf]

On 1/27/2020 at 2:46 PM, Cristian.Fatu said:

Hello,

The maximum sample rate for the chip on ZmodADC1410 (AD9648) is 105 MSPS and the IP is designed for 100MSPS.

This is the only available reference design.

What sample rates do you need?

is it possible to capture 50ms per channel simultaneously on 3 channels using the Eclypse-7 + 2 X ZmodADC1410?

[Cristian.Fatu]

Yes, it is possible.

Using two ZmodADCs will ensure that you can use 3 channels (from the total of 4 available). 

Regarding the sample rate, sampling at 50 ms here are some thoughts: The IP is sampling at 100MSPS, which is one sample at 10ns. Because you only need 50 ms sampling (which is multiple of 10 ns) you should only keep one sample out of 5000000. This can be easily implemented using a counter.