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Recording never stops in Zybo Z7-20 DMA Audio Demo/Vivado 2018.2


cwerner77

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Hello,

my name is Christian and I am refreshing my VHDL skills. That's why I have bought a Zybo Z7-10 board half a year ago. With this board everything worked smoothly -- including the Zybo-Z10-DMA demo. Thank you, Digilent, for this excellent product!

Two weeks ago, I have bought the next bigger board, the Zybo Z7-20. With this, the Zybo-Z20 DMA Audio Demo gets locked up while recording: Using BTN2 for playback works as expected: Playback stops after a few seconds. When you press BTN1 or BTN3, the recording starts, but never stops. If you then press any of the other buttons, you receive the message "still recording...".

To me this looks like there is something wrong with the interrupt indicating that the S2MM DMA transfer is complete.

Please note, that I am not failing to build a new working bitstream in Vivado; I am failing to get the SDK demo running using the pre-built bitstream from the repo! However, if I rebuild the bitstream in Vivado I get identical results. I have already checked the following in order to resolve the issue:

These are the steps to reproduce the problem:

Since the Zybo-Z7-10-DMA demo project is working flawlessly on my Zybo-Z10 board, I think that it is rather unlikely that something is wrong with my development environment or the way that I set up the project in the SDK.

I am struggling for almost one week with this issue. Any helpful hint is very welcome! ?

Has anybody managed to get this demo running on the current version of the Zybo Z7-20? Has anybody the same problem?

Best regards,

Christian

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Hi @cwerner77,

I tried to reproduce the problem but unfortunately I could not. You are right though in your assumption, it most likely is a DMA related problem, it expects to receive a certain amount of samples and if the stream is interrupted for some reasons it will stop. If you can record the first time and play back as well then it's most likely not an Audio codec issue.

The most likely problem is that the DMA is either in an error state or the IP is no responding to the DMA request. There is a bug in the Demo that if you reprogram the FPGA without resting the board the DMA will hang. Either way I would recommend trying to reset the DMA controller before every playback or record. This would narrow down the search for why it does not work. This can be done with the XAxiDma_Reset() function.

I'm also assuming at this point that you did not change anything in the Vivado project or the SDK sources. If you did please let me know, it is unlikely but it might effect the demo.

- Ciprian

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Hi Ciprian,

thank you for your hints -- these have finally fixed the problem!

If I start the board with JP5 set to QSPI the factory programmed board demo runs from flash memory. When I then reprogram the Zynq with the bitstream for the Zybo-Z20-DMA demo, the problem occurs. I have also tried to reset the DMA controller with XAxiDma_Reset() at the beginning of fnAudioRecord() as well as at the beginning of fnAudioPlay() -- this did not fix the problem. The I2S IP and/or the DMA controller seem to come up and remain in an error state if the Zynq gets reprogrammed after running the board demo.

If I start the board with JP5 set to JTAG the Zynq just waits for being programmed after powering up. When I then program the Zynq with the bitstream for the Zybo-Z20-DMA demo, everything runs fine! (BTW: on my Zybo-Z10 JP5 is also set to JTAG).

I am still not sure what exactly causes the problem, but it is certainly closely related with the "reset bug" you have mentioned.

Thank you again! I wish you happy Christmas holidays! ?

Christian

Edited by cwerner77
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On 12/21/2019 at 5:32 PM, cwerner77 said:

Hi Ciprian,

thank you for your hints -- these have finally fixed the problem!

If I start the board with JP5 set to QSPI the factory programmed board demo runs from flash memory. When I then reprogram the Zynq with the bitstream for the Zybo-Z20-DMA demo, the problem occurs. I have also tried to reset the DMA controller with XAxiDma_Reset() at the beginning of fnAudioRecord() as well as at the beginning of fnAudioPlay() -- this did not fix the problem. The I2S IP and/or the DMA controller seem to come up and remain in an error state if the Zynq gets reprogrammed after running the board demo.

If I start the board with JP5 set to JTAG the Zynq just waits for being programmed after powering up. When I then program the Zynq with the bitstream for the Zybo-Z20-DMA demo, everything runs fine! (BTW: on my Zybo-Z10 JP5 is also set to JTAG).

I am still not sure what exactly causes the problem, but it is certainly closely related with the "reset bug" you have mentioned.

Thank you again! I wish you happy Christmas holidays! ?

Christian

Can you please share your code and also, can you please tell me how to set JP5 to JTAG. I am getting the same error. I am having ZyboZ7-10

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