Dividing in Verilog.

[skylape]

Hello guys,

I have a question regarding dividing operation in FPGA(Verilog). Given that I cant use "/" operator, what are the method to divide when the two operands are 16 bit register and when one is 16 bit register and one is a constant? Also is there like a quotient and remainder register like those in AVR?

Thank you. 

[hamster]

If you are dividing by a  constant to can multiply by the inverse. If you only have a small number of different divisors you could consider a lookup table of inverses. 

Otherwise you need to implement a binary division algorithm yourself, to meet your throughput and latency needs.

Division by arbitrary numbers is quite expensive - best avoided if at all possible.

[skylape]

23 hours ago, hamster said:

implement a binary division algorithm yourself

Would something like this work https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf ? It is a IP wizard from xillinx. 

[hamster]

2 hours ago, skylape said:

Would something like this work https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf ? It is a IP wizard from xillinx. 

It may well do, but not knowing *all* the details of what you are doing means I can't offer you useful advice.