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synchronization issues at certain frequences with AnalogDiscovery2 using SDK on Digital Outputs


spri

Question

I have been using the AnalogDiscovery2 with a custom python application built with the SDK to provide synchronous control to several lab instruments. I recently discovered that at certain sample rates, my signals aren't actually synchronized. I've stared at the code for two days and can't find my error, so I'm reaching out for help!

The Q-clock runs at frequency that is an integer multiple of the X-clock. In most cases, the two clocks remain synchronized indefinitely. However, at some frequencies, the Q-clock starts synchronized but begins to drift with respect to the X-clock, so after a few seconds they are no longer synchronized. I thought this might be due to a rounding issue when using a frequency by which the system clock isn't divisible (ie, at 30hz a remainder gets cut off and the clock gets 'off' by 1/3ms every cycle). However, I don't  have this issue at other non-divisible frequencies (like 60, 150 and 300 hz). 

Here is the code in question:

##Qclock
#normal low with high pulses at qrate = n*xrate where n is an int
dwf.FDwfDigitalOutEnableSet(hdwf, c_int(1), c_int(1)) # enable dIO pin 1
dwf.FDwfDigitalOutDividerSet(hdwf, c_int(1), c_int(int(hzSys.value/(100*qrate)))) # divider=internal clock/ (100counts*frequency)
dwf.FDwfDigitalOutIdleSet(hdwf, c_int(1), DwfDigitalOutIdleLow)  #set idle to low
dwf.FDwfDigitalOutCounterSet(hdwf, c_int(1), c_int(int(100-qcount)), c_int(qcount))) # set counts low, counts high 
dwf.FDwfDigitalOutCounterInitSet(hdwf, c_int(1), c_int(1), c_int(0)) #pin1, start HIGH, initial counter = 0
            
##Xclock
#normal low with high pulses at xrate
dwf.FDwfDigitalOutEnableSet(hdwf, c_int(2), c_int(1)) # enable dIO pin 2
dwf.FDwfDigitalOutDividerSet(hdwf, c_int(2), c_int(int(hzSys.value/(100*xrate)))) # divider=internal clock/ (100counts*frequency)
dwf.FDwfDigitalOutIdleSet(hdwf, c_int(2), DwfDigitalOutIdleLow)  #set idle to low
dwf.FDwfDigitalOutCounterSet(hdwf, c_int(2), c_int(int(100-xcount)), c_int(xcount)) # set counts low, counts high from duty cycle
dwf.FDwfDigitalOutCounterInitSet(hdwf, c_int(2), c_int(1), c_int(0)) #pin2, start high, initial counter = 0

 

Here is a picture of the external oscilloscope showing the 'drift' between the signals after running for a few seconds: (blue =Qclock at 60hz, yellow=Xclock at 30hz), the rising edges of every other blue pulse should line up with the yellow ones.  

image.png.0188ebc90dce1758a3df9a13c0f3c2d8.png

Again, this only happens at certain frequencies.  Most of the time (at nice, even numbers) everything lines up perfectly. 

Any help would be appreciated! Thanks! 

 

 

 

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Hi @spri

The drift is cause by the resulting dividers, like:
100e6Hz/30/100Hz ~= 33M333 ~= 30.(00030) Hz
100e6Hz/60/100Hz ~= 16M666 ~= 60.00240 Hz

You should use for 30Hz division of 33M332, which will be 2x of 16M666. For other frequencies, the divider to have a low common multiple.

You could also set run-length to longest or common multiple period, like for 30/60Hz:
dwf.FDwfDigitalOutRunSet(hdwf, c_double(1.0/30))
dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(0))

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