How to add a delay given a 50 Mhz clock

[TJ]

How do add a 1 second delay when verifying each RAM data/address one at a time last process of code?

Sparten -3E using xc3s100 device.  Xilinx P.20131013 version ISE Project Navigator.   Regarding the following process if I comment out two of the three then the one not commented out reads the correct LCD values based on the RAM reading of dataout and address.  Any idea how to put in about a 1 second delay between each of the below so that I can see the LCD values change everytime I confirm each correct reading from RAM:

process   -- Which LCDs to turn on based on reading data from RAM process

begin  -- How to add a one second delay between each time I read specific data from RAM

          if DataOut1 = x"AA" and Address1 = x"04" then an<="0000"; ssg<="11111001"; end if; --confirmed "1" 

          if DataOut2 = x"55" and Address2 = x"06" then an<="0000"; ssg<="10100100"; end if; --confirmed "2" 

          if DataOut3 = x"78" and Address3 = x"08" then an<="0000"; ssg<="10110000"; end if; --confirmed "3"  

end process;

 ----------------------------------------

The below is my VHDL code:

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

 

entity RAM is

    Port ( 

   mclk, Reset, WriteEn, Enable         : in  STD_LOGIC; 

an                                   : inout STD_LOGIC_VECTOR (3 downto 0);  --LCDs

       ssg                                  : out STD_LOGIC_VECTOR (7 downto 0)  -- 7 Segment Display

    );

end RAM;

 

architecture Behavioral of RAM is

    type Memory_Array is array (0 to (2 ** 8) - 1) of STD_LOGIC_VECTOR (7 downto 0);

    signal Memory : Memory_Array; 

signal DataIn, Address, DataOut         : STD_LOGIC_VECTOR (7 downto 0);  

    signal DataOut1, DataOut2, DataOut3     : STD_LOGIC_VECTOR (7 downto 0);

signal Address1, Address2, Address3     : STD_LOGIC_VECTOR (7 downto 0);

  

begin

  

process (mclk) -- Write process

    begin

        if rising_edge(mclk) then

            if Reset = '1' then -- Clear Memory on Reset

                Memory <= (others => (others => '0'));

            elsif Enable = '1' then

                if WriteEn = '1' then -- Store DataIn to Current Memory Address 

Address<=x"04"; DataIn<=x"AA"; Memory(to_integer(unsigned(Address))) <= DataIn;   

Address<=x"06"; DataIn<=x"55"; Memory(to_integer(unsigned(Address))) <= DataIn;   

Address<=x"08"; DataIn<=x"78"; Memory(to_integer(unsigned(Address))) <= DataIn;   

                end if;

            end if;

        end if;

    end process;

  

process (mclk) -- Read process

begin

  if rising_edge(mclk) then        

   if Enable = '1' then

      if WriteEn = '0' then -- Read Memory

Address1 <= x"04"; DataOut1 <= Memory(to_integer(unsigned(Address)));

Address2 <= x"06"; DataOut2 <= Memory(to_integer(unsigned(Address)));

Address3 <= x"08"; DataOut3 <= Memory(to_integer(unsigned(Address)));

      end if;      

    end if; 

  end if;

end process;

 

 

process   -- Which LCDs to turn on based on reading data from RAM process

begin

          if DataOut1 = x"AA" and Address1 = x"04" then an<="0000"; ssg<="11111001"; end if; --confirmed "1" 

if DataOut2 = x"55" and Address2 = x"06" then an<="0000"; ssg<="10100100"; end if; --confirmed "2" 

if DataOut3 = x"78" and Address3 = x"08" then an<="0000"; ssg<="10110000"; end if; --confirmed "3"  

end process;

 

end Behavioral; 

 

Thanks much.

[JColvin]

Hi TJ,

I have asked some of our applications engineers about this to see if they have any experience with it.

Thanks,
JColvin

[artvvb]

TJ,

The way I would generally go about adding sequential logic to an FPGA design would be to use a counter and a case statement. The counter would be driven by a clock divided down to 1Hz, and roll over once a maximum is hit. Since you have three statements to check, the counter would roll over from 2 to 0.

On 4/18/2016 at 8:12 PM, TJ said:

process   -- Which LCDs to turn on based on reading data from RAM process

 

begin  -- How to add a one second delay between each time I read specific data from RAM

          if DataOut1 = x"AA" and Address1 = x"04" then an<="0000"; ssg<="11111001"; end if; --confirmed "1" 

 

          if DataOut2 = x"55" and Address2 = x"06" then an<="0000"; ssg<="10100100"; end if; --confirmed "2" 

 

          if DataOut3 = x"78" and Address3 = x"08" then an<="0000"; ssg<="10110000"; end if; --confirmed "3"  

 

end process;

would become

process

begin

case (count)

"0": statement #1

"1": statement #2

"2": statement #3

endcase

end process

Thanks,

Arthur

[TJ]

Hello Arthur,

Thanks much.  How would you recommend that I implement the counter and make it 1 second in the vhdl code?  I am not understanding. 

Thanks,

TJ

 

[TommyK]

Hi TJ,

It's very simple to create a counter that counts at 1 second. If you're using the 50MHz clock, you would make a std_logic_vector(25 downto 0), so it could count up to 50000000. Then every rising edge you increment it. If your counter == 50000000, then you have hit 1 second, so reset your counter to 0 and do whatever you need to do every 1 second.

Check out Learn.Digilentinc.com for a great introduction course in FPGAs. This section gives a great intro to counters!

Hope this helps!

[artvvb]

TJ,

I'd take a look at this project: https://learn.digilentinc.com/Documents/262

In step 2.4 it has you set up a flip flop controlled by a counter. This flip flop could be replaced with another counter. By changing the max count of the faster counter, you can control how often the slower counter updates. Swapping out the flip flop means you'd have to double the constant number being used to create a 1Hz clock.

Thanks,

Arthur