I2C tristate pins without board definition files

[Phil]

I have the Arty A7-100T and have successfully built and run a project using the PMOD RTCC module, which uses the I2C interface.

I modified the project to use the I2C pins on connector J3 of the Arty and enabled the pullup resistors.  I wired the SCL & SDA pins to the PMOD RTCC and all is good.  It runs the same as if connected to the PMOD connector.

So now I am trying to build my project without using the I2C defined port that is in the board definition files.  I want to connect directly to the 6 control and data lines that make up the I2C port on the AXI IIC IP and I want to be able to use any of the available I/O pins on the board for SCL & SDA (I realize that I will need external pullup resistors unless the internal pullups available in the FPGA are sufficient).

The problem I am having is that I get failures during synthesis that seem to not like me trying to use bi-directional tristate pins for SCL and SDA.

I have a Verilog file that I am using for the bi-directional tristate control:

    module tristate(IO_Data, Tx_Data, Rx_Data, Tri_En);

        inout  IO_Data; // bidirectional data line

        input  Tx_Data;
        output Rx_Data;
        input  Tri_En;
 
        assign IO_Data = Tri_En? 1'bz:Tx_Data;
        assign Rx_Data = IO_Data;

    endmodule

 

This is what it looks like wired up:

These are the constraints on the 2 pins:

set_property PACKAGE_PIN L18 [get_ports scl]
set_property IOSTANDARD LVCMOS33 [get_ports scl]

set_property PACKAGE_PIN M18 [get_ports sda]
set_property IOSTANDARD LVCMOS33 [get_ports sda]

This is the type of error I get:

[Designutils 20-1595] In entity system_tristate_0_1, connectivity of net IO_Data cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: 
   inout IO_Data

Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal.

 

My questions are:

1) Should I be able to connect I2C in this manner without having the port defined in a board definition file?

2) If so, any suggestions to correct my design or how to eliminate the errors I'm seeing?

3) Is there a tristate buffer primitive or IP that I should be able to use here (I cannot find one, which is why I attempted to create my own here)?

4) The PMOD RTCC module does not have pullup resistors on SCL & SDA.  When using it with the PMOD connector and the board definition files it works.  Are the internal FPGA pullup resistors enabled somewhere?  I could not find that anywhere in the PMOD definition files or the Arty board definition files.

 

[artvvb]

Hi @Phil

1. Yes.

2. The error appears to be coming from Vivado generating invalid VHDL syntax for this specific scenario. Make sure that your  HDL wrapper file is in Verilog, rather than VHDL. Here is a thread on the Xilinx Forums with some more detail.

3. IOBUFT can be used from within an Verilog module, but cannot directly be instantiated in IPI, as far as I know. It is likely what is being inferred by your module. This should also work though: you can directly make the AXI IIC's IIC interface port external (by right clicking on the interface port and selecting "Make External"), as seen in the screenshot below:

At least when using a Verilog wrapper file, this results in the ports being generated like so:

4. The Pmod RTCC IP core enables the I2C pullups on its IO buffers. This can be done for your own ports in an XDC file like so:

set_property PULLUP TRUE [get_ports <port>]

Thanks,

Arthur

[Phil]

@artvvb

Arthur, thanks for the detailed reply.  This is the information I needed to move forward.  My HDL wrapper is Verilog, which threw me off when I got the error messages about VHDL.  In the top level settings the target language is set for Verilog.  I'm not aware of another setting somewhere that would affect this.

From the example you provided, when the IIC port is made external and the HDL wrapper is updated to account for this, I did not realize before that the IOBUF buffers were instantiated and that the _io signals are then made available to make my pin assignment in my .xdc file.  This is the information I needed and I can see how the tristate is being handled.  I have tested this by assigning pins on different connectors than the ones pre-defined for I2C and PMOD in the board definition files.  After adding the pullup constraints it all works fine and I can now use other available I/O pins.