tip.can19 Posted December 5, 2019 Share Posted December 5, 2019 Hi, I was looking to know what CYINIT is in CARRY4 block and it's role? I assume the CI is the carry in from previous cascade, but not sure. Any idea on this? I use Xilinx 7-series device in Vivado 2019.1, we can refer UG953 (page.290) for CARRY4 block. Thank you, Link to comment Share on other sites More sharing options...
JColvin Posted December 5, 2019 Share Posted December 5, 2019 Hi @tip.can19, The CYINIT pin appears to be an initialization bit, presumably to have the IP block to prepare itself for incoming data. It looks like this Xilinx thread addresses this in more detail. Thanks, JColvin Link to comment Share on other sites More sharing options...
tip.can19 Posted December 6, 2019 Author Share Posted December 6, 2019 Hi @JColvin Thank you! I have now understanding of CYINIT. Regards, Link to comment Share on other sites More sharing options...
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tip.can19
Hi,
I was looking to know what CYINIT is in CARRY4 block and it's role? I assume the CI is the carry in from previous cascade, but not sure. Any idea on this?
I use Xilinx 7-series device in Vivado 2019.1, we can refer UG953 (page.290) for CARRY4 block.
Thank you,
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