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Abuzar

Accessing XADC pins of FPGA for Analogue to Digital converter

Question

Hello,

I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets".

Design is below:

design.JPG.2ea14bae90f052e3e8f4effdbaa5d179.JPG

As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. 

error.JPG.5f58216b9c9e070b6ef7ae9781071004.JPG

Pin assignment are as under for VC707

pins.thumb.JPG.e09431704280862f68db5ae981965760.JPG

Schematics diagram for VC707

xadc.JPG.81bbc07e88b69c13f0120429306734b5.JPG

 

Any help will be appreciated.

Thanks,

Edited by Abuzar
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1 answer to this question

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Hi @Abuzar

The VP and VN pins are dedicated analog inputs and should not be connected to the ILA. Only the auxiliary analog inputs may be used as digital I/O, but even then, cannot be used for both analog and digital I/O at the same time. Page 16 of the XADC User Guide has some more information.

Thanks,

Arthur

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