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Accessing XADC pins of FPGA for Analogue to Digital converter



I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets".

Design is below:


As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. 


Pin assignment are as under for VC707


Schematics diagram for VC707



Any help will be appreciated.


Edited by Abuzar
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Hi @Abuzar

The VP and VN pins are dedicated analog inputs and should not be connected to the ILA. Only the auxiliary analog inputs may be used as digital I/O, but even then, cannot be used for both analog and digital I/O at the same time. Page 16 of the XADC User Guide has some more information.



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