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ZYBO Z7 Pmod frequency limits?


Triston

Question

Hello Everyone,

I'm a bit new to ZYNQ devices, and embedded systems in general.

I'm trying to get a 20 MHz SPI to come out of PMOD JA, and it is indeed coming out. The problem is at the frequency I have it set to (20MHz), the square wave seems to be slewed out ( All triangles, no squares). I increased the Slewrate  in the .xdc file, and the drive current, but I still have the same problem. When I lower the frequency it tends to be more square (as you'd expect), but at 20 MHz, it is just not happy, as can be seen in the picture below. The Clock is in Red  and the MOSI data in Blue.

I assumed that the PMOD ports could handle this frequency, was i just wrong?

 



 

ZYBO Clock 20MHz.png

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Hi,

most likely there are resistors in the PMOD port for protection (check the schematic). If I recall correctly, you may find one PMOD port without resistors.

Other GPIOs will be fast enough for a clean square wave.

BTW, it may be that your scope probe causes most of the capacitive loading that causes the damage to the edges. Try setting it to 1:10 mode (more noise on the scope but less loading to the source).

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Hello xc6lx45,

I changed the pmod  to the JC port and the signal was a bit better but still, not great. The mode of the probes were already at 1:10, the probes were compensated, and the load capacitance on the probes are only 6pF. Still the signals are a bit better. Thanks for the tip. 

Apparently the JC and JA pmod ports have no resistance in thier port paths.

 

ZYBO Clock 20MHz Jc Pmod_SRhigh_DRIVE16mA.png

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The protection resistors and any load capacitance (pin, trace, probe and most importantly SPI slave) will form an RC low-pass filter. JC and JD do not have protection resistors, which is why you see an improvement. On those ports, it is the output impedance of the driver is what is limiting you. By increasing drive, you lower the output impedance.

You can try other I/O standards, but you are limited to those compatible with the 3.3V bank supply.

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