Jump to content
  • 0

making differential output Clock


youngpark

Question

Hi there!

I'm trying to make  differential clock(100MHz from oscillator) to differential clock output(40MHz differential)image.thumb.png.7e6ad560084f1b37530b6664af632708.png

clk_100M_P&M is connected to external crystal oscillator(input)  and I allocated clk_40_P&M to PIO port(output).

clk_front , clk_back is for check point. when I checked, the result was  clk_front : 100MHz  & clk_back : 40MHz . However,  clk_40_P &N port didn't output some waveform.

I have no idea what's the problem.

1st trial : clk_front & back : LVCmos33  and clk_40_P & N :  LVDS25      ->    result : LVCmos33,(bank34) clk_front & back (success)  and (bank35) clk_40_P & N : LVDS25 ( failed ) 

2nd trial clk_front & back : LVCmos25  and clk_40_P & N :  LVDS25      ->    result : LVCmos25 ,(bank35) clk_front & back (success)  and (bank35) clk_40_P & N : LVDS25 ( failed )

 

thank you for your help!

 

 

Link to comment
Share on other sites

5 answers to this question

Recommended Posts

Hi @youngpark,

Well I don't know for sure why its not working for you but I would recommend a different approach. The most important thing for you is to make sure that the clock gets propagated throug the design using the clock path and this is done using an ODDR primitive. Therefore I suggest using this aproch:1234554836_Screenshotfrom2019-11-2916-07-34.thumb.png.38aedf6cb88701d167cc79291602ba1b.png

The clock forwarder can be found on our github in the vivado-library.

You will also have to constrain it. For this please take a look in the ug903 provided by Xilinx specifically starting page 31.

Good Luck

-Ciprian

Link to comment
Share on other sites

Thank you for your advice, but even when I followed your tips, the result was same(failed).

Now I wonder if the cause of this problem is local power. The local power supply has only 3.3V, 1.8V and 1.0V. And there are no 2.5V power. So LVDS_25's 2.5V seems like not generatred.  

I suspect this is the cause.

I'm curious about your opinion.

Thank you.

-S. Park-

image.png

Link to comment
Share on other sites

@youngpark,

The CmodS7 has only 3.3V I/O banks.  You will not be able to generate anything other than 3.3V outputs.  I took a quick glance at the schematic and didn't see any length matched GPIO pairs.  Depending upon the performance you need, this is often a requirement.  You might still be able to break the rules and create two LVCMOS3V3 digital outputs, each opposite each other, to make this happen but it doesn't appear as though the board was designed to support such a requirement.  If you choose to do that, then let me recommend you use two ODDR primitives, each with opposite polarity, to try to make this work.  That'll at least help you get the timing right.

Dan

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...