Interfacing microphone and audio-out on Nexys4

[paulleons]

 

Hi,

I am trying to use microphone and audio-out of Nexys 4 board from Digilant. I have the following questions:

1. I implemented the refernce audio design provided by digilant which records audio for 5 seconds and play-back the recording from RAM. I noticed that both the interface namely micro-phone and audio-out operate on same clock domain and PDM interface. I tried to by-pass the RAM by directly connecting micro-phone output to audio-input (after 2 pipeline stages). But the design does not work as expected. Any thoughts on this will be appreciated. 

2. I would also like to process the data received in FPGA via PDM. How do I convert this to N-bit digital signal of certain frequency which corresponding to the analog signal ? Should I do a moving average over certain terms. If so, how many terms? The figure 28 in the user-guide doesn't seem to be very clear. 

Thanks,

Paul

 

[JColvin]

Hi paulleons,

I have asked some of our applications engineers about this; they will get back to you here on the Forum.

Thanks,
JColvin

[mskreen]

Hello paulleons,

To address your first question, when connecting the microphone input to your mono audio output how did your project not work as expected? The verilog code below might help serve as a simple reference if you're still having issues. This module samples at N=1 bit, so every PDM bit is output to the PWM out. Figure 28 is an incorrect diagram. If you would like to capture your samples with a certain bit number just offset your samples by 180 degrees. For example if your samples are being taken with a width of 128 clock cycles then when sample 1 is at it's 64th cycle, sample 2 should then begin taking PDM information. With these samples you can easily use their PDM counts in a comparator to output a PWM signal for the audio jack.

`timescale 1ns / 1ps

module Mic_Demo(
    output anout,
    output ampSD,
	output sclk,
	output ncs,
	input sdata,
    input clk
    );

reg [4:0]clk_cntr_reg;
reg pwm_val_reg;

always @(posedge clk)
begin
    clk_cntr_reg <= clk_cntr_reg + 1;
end

always @(posedge clk)
begin
    if(clk_cntr_reg == 5'b01111) begin
        pwm_val_reg <= sdata;
    end
end

//sclk = 100MHz / 32 = 3.125 MHz
assign sclk = clk_cntr_reg[4];

assign anout = pwm_val_reg;
assign ncs = 1'b0;      //mic LRSel
assign ampSD = 1'b1;


endmodule

 

Hope this helps.

Mikel

[paulleons]

On 4/28/2016 at 5:23 PM, mskreen said:

Hello paulleons,

To address your first question, when connecting the microphone input to your mono audio output how did your project not work as expected? The verilog code below might help serve as a simple reference if you're still having issues. This module samples at N=1 bit, so every PDM bit is output to the PWM out. Figure 28 is an incorrect diagram. If you would like to capture your samples with a certain bit number just offset your samples by 180 degrees. For example if your samples are being taken with a width of 128 clock cycles then when sample 1 is at it's 64th cycle, sample 2 should then begin taking PDM information. With these samples you can easily use their PDM counts in a comparator to output a PWM signal for the audio jack.

`timescale 1ns / 1ps

module Mic_Demo(
    output anout,
    output ampSD,
	output sclk,
	output ncs,
	input sdata,
    input clk
    );

reg [4:0]clk_cntr_reg;
reg pwm_val_reg;

always @(posedge clk)
begin
    clk_cntr_reg <= clk_cntr_reg + 1;
end

always @(posedge clk)
begin
    if(clk_cntr_reg == 5'b01111) begin
        pwm_val_reg <= sdata;
    end
end

//sclk = 100MHz / 32 = 3.125 MHz
assign sclk = clk_cntr_reg[4];

assign anout = pwm_val_reg;
assign ncs = 1'b0;      //mic LRSel
assign ampSD = 1'b1;


endmodule

 

Hope this helps.

Mikel

Thanks Mikel and JColvi. 

I tried your code and unfortunately, it did not work. I created a small wrapper code for the code provided and the design behaved the same as before(attached wrapper code along with the post). On-chip data capture using ILA core was also done and the capture is also attached with the post. It shows that PDM data is indeed fed back to PWM output to audio-out. However, I cannot hear anything from the audio output. I was wondering if the code provided was ever tested in actual hardware.If so, could I get access to that Xilinx project? 

Also, if figure 28 in the reference guide is wrong, it would be great if you could provide another figure along with a detailed description so that it's becomes more clear. 

 

Wrapper code:

module microphone_audio_out_top (
    input  logic clk_i        ,
    input  logic rstn_i       ,

    output logic pdm_clk_o    ,
    input  logic pdm_data_i   ,
    output logic pdm_lrsel_o  ,

    output logic pwm_audio_o  ,
    output logic pwm_sdaudio_o
);

Mic_Demo Mic_Demo_inst
(
    .anout  (pwm_audio_o    ),            
    .ampSD  (pwm_sdaudio_o  ),
    .sclk   (pdm_clk_o      ),
    .ncs    (pdm_lrsel_o    ),
    .sdata  (pdm_data_i     ),
    .clk    (clk_i          )
);

endmodule

microphone_audio_out_top.sv

[TommyK]

Hi paulleons,

It's strange that your code doesn't work. Have you mapped the pins correctly in your .xdc file? This code is taken out of the Nexys 4 GPIO Demo. Have you tried running just the individual module? I tried it out and it worked fine on my Nexys 4. Also, I read somewhere that System Verilog isn't 100% supported in Vivado, although your wrapper code should still work. As for the figure, I'll see if I can find someone who can fix that.

 

Hope this helps!

Tommy