First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home....
NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E)
Day 1:
Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned.
Day 2:
Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting.
Day 3:
Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for.
Day 4:
Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic)
Day 5:
Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage.
(This was another step to validate FPGA platform functionality & correctness).
Day 6:
Re-code and re-sim DA1 Verilog. Works as expected.
Day 7:
Integrate code onto XEM3005 - still no joy.
Probe with oscilloscope:
Power good - 3.3V, rock solid
Ground good: little to no noise.
Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable.
Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time)
DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think)
It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?)
Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file.
Double- and triple-checked that the D0 and D1 ports are set up as inputs.
Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC)
Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical.
Day 8:
Just got home - did some double checking and disconnected the PMOD outputs from the FPGA:
With the FPGA disconnected, the signals look pretty darned good:
Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash...
This is clearly (I think) an FPGA setup problem..
So, here I am... Looking for clues. Anyone have any?
Question
tomii
Hey all,
First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home....
NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E)
Day 1:
Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned.
Day 2:
Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting.
Day 3:
Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for.
Day 4:
Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic)
Day 5:
Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage.
(This was another step to validate FPGA platform functionality & correctness).
Day 6:
Re-code and re-sim DA1 Verilog. Works as expected.
Day 7:
Integrate code onto XEM3005 - still no joy.
Probe with oscilloscope:
Power good - 3.3V, rock solid
Ground good: little to no noise.
Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable.
Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time)
DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think)
It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?)
Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file.
Double- and triple-checked that the D0 and D1 ports are set up as inputs.
Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC)
Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical.
Day 8:
Just got home - did some double checking and disconnected the PMOD outputs from the FPGA:
With the FPGA disconnected, the signals look pretty darned good:
Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash...
This is clearly (I think) an FPGA setup problem..
So, here I am... Looking for clues. Anyone have any?
Thanks in advance
Link to comment
Share on other sites
4 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.