Question

Hello,

I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz.

It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle.

Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing??

Looking forward to you suggestions and other similar references.

Thanks in advance

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Hi @Padmanabhan,

There could be several botlenecks in your design. Add an ILA to the DA SPI interface, or scope the Pmod pins to see what is the utilization rate of the interface. If there are pauses in data transfer, upstream masters could be sending data too slow. The AXI quad spi controller has options for FIFO buffering and a different AXI interface. AXI lite is not meant for high-bandwidth data transfer, and AXI MM can be used instead. The processor caches can also have an impact.

 

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