• 0

Removing debug logic of pcam-5c reference design


Go to solution Solved by elodg,

Question

Hello,

I'm trying to modify the pcam-5c design for the Zybo board (Vivado 2017.4).
The design takes up a lot of logic for debug especially in MIPI_CSI2_Rx.vhd.
I tried removing this logic by un-checking the "Debug Module" box of the "MIPI CSI-2 Receiver" core inside the supplied block design.

I saved the design and re-run synthesis - which failed with the following message :

Quote

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

Re-checking the "Debug Module" box are re-synthesizing didn't solve the problem.

The only thing that fixed the problem is copying the \src\bd\system\ip\system_MIPI_CSI_2_RX_0_0 folder from a mirror ( untouched ) design.

2 questions:

1. How did un-checking the "Debug Module" box cause the design to break in such irreversible way?
2. How can I reliably remove the ILA debug logic ?

error.JPG

unselected.JPG

Link to post
Share on other sites

23 answers to this question

Recommended Posts

  • 0
  • Solution
$ git clone https://github.com/Digilent/Zybo-Z7-20-pcam-5c.git
$ git checkout v2018.2-2
$ git submodule init
$ git submodule update
$ python digilent-vivado-scripts/git_vivado.py checkout

This will re-create the Vivado project for the block design sources. Documentation for the scripts here: https://github.com/Digilent/digilent-vivado-scripts/blob/7b4d88aaa3c2c760167b2c563942f56e4a4cfce1/README.md.

Link to post
Share on other sites
  • 1

This is a bug in Vivado which does not properly re-generate all the sources for the IP when it's re-customized. Resetting output products, clearing cache does not help. One possible workaround is to export bd to a tcl, delete the block design and source the tcl to re-create it from scratch.

However, I already gave another possible way of doing this: checking out the source files and using the Python digilent-vivado-scripts to re-create the project. This workflow seems to work, as opposed to using the generated project from release.

I created a commit to disable the debug module in future releases, as it makes more sense for the majority of our users. This will be picked up only in the next release cycle.

Link to post
Share on other sites
  • 0

I did a git checkout v2017.4 and re-generated the Vivado project in 2017.4. It asked for IP upgrade and  I had to create a wrapper for the block design manually (which I should not have had to do), but Synthesis and Implementation worked.

Could you try the 2018.2 release too in Vivado 2018.2 and see if it works.

Link to post
Share on other sites
  • 0

Hi,

1. If you downloaded the 2017.4 project version from GIT - and tried to compile it in the same version - why did it ask for an IP upgrade ?

2. Did you try to un-check the "Debug Module" box for the MIPI CSI-2 and re-compile ? Did it work ?

 

Edited by bitslip
Link to post
Share on other sites
  • 0

1. I think it is either a failed project upgrade or the submodule commit being out of sync with the main repo. This should not happen in the 2018.2 release, which is why I recommend you try it.

2. Of course, that was the whole point of your question.

Link to post
Share on other sites
  • 0

Thanks.

I'll try it with 2018.2

Meanwhile. I managed to workaround the problem by accessing manually changing the HDL inside file: system_MIPI_CSI_2_RX_0_0.vhd

Which is located in:

C:\Zybo-Z7-20-pcam-5c-2017.4-1\src\bd\system\ip\system_MIPI_CSI_2_RX_0_0\synth\system_MIPI_CSI_2_RX_0_0.vhd

 

 

 

Link to post
Share on other sites
  • 0
$ git worktree add ../Zybo-Z7-20-pcam-5c_2018_2 v2018.2-2
$ cd ../Zybo-Z7-20-pcam-5c_2018_2/
$ git submodule init
$ git submodule update
$ python digilent-vivado-scripts/git_vivado.py checkout
Warning: Files and directories contained in C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj may be overwritten. Do you wish to continue? Y/N? Y
Checking out project Zybo-Z7-20-pcam-5c_2018_2.xpr from repo Zybo-Z7-20-pcam-5c_2018_2

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script 'C:/Users/rogyorge/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
INFO: [Common 17-1463] Init.tcl in C:/Users/rogyorge/AppData/Roaming/Xilinx/Vivado/init.tcl is not used. Vivado_init.tcl is already sourced.
source C:/git/Zybo-Z7-20-pcam-5c_2018_2/digilent-vivado-scripts/digilent_vivado_checkout.tcl -notrace
INFO: Creating new project "Zybo-Z7-20-pcam-5c_2018_2" in C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 350.289 ; gain = 119.281
INFO: Capturing board information from C:/git/Zybo-Z7-20-pcam-5c_2018_2/project_info.tcl
INFO: Configuring project IP handling properties
INFO: Setting IP repository paths
INFO: Refreshing IP repositories
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-Z7-20-pcam-5c_2018_2/repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
update_ip_catalog: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 408.137 ; gain = 57.848
INFO: Adding HDL sources
INFO: Adding XCI IP sources
INFO: Adding constraints
INFO: Rebuilding block design from script
INFO: [BD_TCL-3] Currently there is no design <system> in project, so creating one...
Wrote  : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd>
INFO: [BD_TCL-4] Making design <system> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "system".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:
digilentinc.com:user:AXI_BayerToRGB:1.0 digilentinc.com:user:AXI_GammaCorrection:1.0 digilentinc.com:ip:MIPI_CSI_2_RX:1.1 digilentinc.com:ip:MIPI_D_PHY_RX:1.3 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:processing_system7:5.5 digilentinc.com:ip:rgb2dvi:1.4 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:v_axi4s_vid_out:4.0 xilinx.com:ip:v_tc:6.1 xilinx.com:ip:xlconcat:2.1  .
INFO: [BD_TCL-6] Checking if the following modules exist in the project's sources:
DVIClocking  .
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-Z7-20-pcam-5c_2018_2/repo'.
create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 639.629 ; gain = 153.918
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/SerialClk(undef) and /rgb2dvi_0/SerialClk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rgb2dvi_0/PixelClk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rst_vid_clk_dyn/slowest_sync_clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /v_axi4s_vid_out_0/vid_io_out_clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /vtg/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk5X(undef) and /video_dynclk/pxl_clk_5x(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef)
Wrote  : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd>
WARNING: [Coretcl 2-176] No IPs found
WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored
WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.
INFO: [digilentinc.com:ip:MIPI_CSI_2_RX:1.1-17] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz
INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.3-17] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS
Wrote  : <C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/system.bd>
VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/synth/system.vhd
VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/sim/system.vhd
VHDL Output written to : C:/git/Zybo-Z7-20-pcam-5c_2018_2/proj/Zybo-Z7-20-pcam-5c_2018_2.srcs/sources_1/bd/system/hdl/system_wrapper.vhd
make_wrapper: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 841.781 ; gain = 97.035
INFO: Configuring synth_1 run
INFO: Setting current synthesis run
INFO: Configuring impl_1 run
INFO: Setting current implementation run
INFO: Project created: Zybo-Z7-20-pcam-5c_2018_2
INFO: Exiting Vivado
INFO: [Common 17-206] Exiting Vivado at Fri Nov 29 11:46:17 2019...

Opened in Vivado proj/*.xpr, unticked CSI-2 Debug module and Generated Bitstream successfully.

Link to post
Share on other sites
  • 0

Hello,

 

I'm using zybo z7 2010,  Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I the following steps.

1. open project

2. change device to zybo z7 7010 

3. update all IPs

4. create HDL

5. synthesis and impliment.

I'm getting no error till here but following critical warnings after open implementation.

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

 

6. generate bit

7. export to hardware (include bitstream)

8. lanch SDK

after this I followed the exact steps given on README file on github.

9. program fpga 

10. and run as debug

I'm getting no error but still not able to get the image on the screen or the menu on the terminal.

Link to post
Share on other sites
  • 0
Quote

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Is a known issue in our D-PHY IP.

 

Quote

I'm getting no error but still not able to get the image on the screen or the menu on the terminal.

If you are getting nothing on the terminal I suspect you messed up something in the Vivado project while porting to 7010. I do not want to sidetrack you, but you could try the latest version of the project (2020.1), which has a 7010 port too: https://github.com/Digilent/Zybo-Z7-SW/tree/10/Pcam-5c/next.

It uses a new project structure and versioning rules. Read this: https://reference.digilentinc.com/reference/programmable-logic/documents/git#vitis_sw_workspaces

 

 

Link to post
Share on other sites
  • 0

 

Hello,

I'm using zybo z7-20,  Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I followed all the steps in https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.30634943.1211223159.1605501220-381318644.1601993729.

The program runs with no error, but I can't get the any image on the screen or the menu on the terminal. 

The video shows my monitor while I'm following demo instruction step. Plz let me the reason why it is not working.

 

Link to post
Share on other sites
  • 0
6 hours ago, Kyle_ISL said:

 

Hello,

I'm using zybo z7-20,  Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I followed all the steps in https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.30634943.1211223159.1605501220-381318644.1601993729.

The program runs with no error, but I can't get the any image on the screen or the menu on the terminal. 

The video shows my monitor while I'm following demo instruction step. Plz let me the reason why it is not working.

 

Sorry but I couldn't replicate you problems, it worked first try for me following the exact same steps as you did.

 

But I can recommend some things you can try to hopefully get the project working properly. 

First you can try resetting the output products by right-clicking the block design file and then clicking "Reset Output Products...".

image.thumb.png.054f94f2a81082f5267026f877387d48.png

Then go to Tools -> Settings... -> IP, press the Clear Cache button and then click OK.

image.png.c7d08bc5062321f757ce6609ebc65e7d.png

image.thumb.png.120cb712f8099fe08c8695296fd3da37.png

Now go to the Design Runs tab, right-click on impl_1 and select Reset Runs. Do the same thing for synth_1 as well.

image.png.c0ab34422db48def5244e328f42552fd.png

After that click on Generate Bitstream and wait a bit for a new bitstream to be completed. If somehow you get some critical warnings telling you that the MIPI_D_PHY_RX_0 IP was packaged with a different board_part you can just ignore those by pressing OK and then clicking on Generate Bitstream again.

Now you should export the new hardware handoff and launch the SDK again (if the SDK is already open you don't have to launch it again).

Right-click on system_wrapper_hw_platform_0  and select Change Hardware Platform Specification to update it to the new hardware handoff.

image.png.4645ea98f80cab05153d3f262133f1ed.png

After that you should clean the entire workspace and then build it all again.

image.png.20ab0d961b1944ccab2aaa9d5786a876.png

Finally, you can program the FPGA and run the application again.

You will hopefully see something like this in your tera term console:

image.png.8544a2127f6d7b67cfa9190ae27392ba.png

Please do let us know if you've encountered other problems or if, after following all these steps, you still couldn't manage to get the application working properly.

Link to post
Share on other sites
  • 0

Hi

1) I present you the schematic of the FMC Pcam Adapter, here I had a question : why the HS-A-P and HS-A-N are inversed ?
Actually the Pin 23 of the « MC20901 » is shown as a positive signal but as an output we can see that they provide a negative signal.
The same for pin 22, normally it will be a negative signals and they put it as a positive signal.
2) Why the signals of LP[A-D]_LANE1_[PN]_LS, and LP[A-D]_CLK_[PN]_LS are unidirectional ? And why the DIR and OE# of the level translators (IC10 : SN74AVC4T245) are hard-wired like that ? In other word Why the DIR and OE are linked to the ground so the direction of the signals will be from FMC to the Camera like shown in the bleu arrow ? , is that direction is correct ? And what the purpose of having direction of the low power signals from the FMC to the cameras ?

Screenshot from 2020-12-07 10-18-59.png

Screenshot from 2020-12-07 10-18-59.png

Link to post
Share on other sites
  • 0

1. Table 8 from the datasheet shows how pins HSx_P and HSx_N can be swapped by the level translator: http://www.meticom.com/resources/Datasheets/MC20901-V1_08.pdf. It has been done for easier routing in layout.

2. LPx_LANE1 and LPx_CLK and uni-directional because the MC20901 can only do low-power reverse communication on either channel A or E, but only on a single channel. This is a transmission mode part of the MIPI D-PHY spec. The decision was made to make LANE0 the one supporting this mode. This is described in https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual?s[]=fmc&s[]=pcam#low-power_reverse_communicationbus_turn-around_bta. Our Pcam 5C does not support low-power reverse com, but some other sensors might.
The direction of communication is opposite of what you described. IC10 with DIR to GND transmits from B to A, or Pcam to FMC.

Link to post
Share on other sites
  • 0

Hi there!

When I open the XPR project file, which is located at 'extracted file location'/lived_proj/Zybo-Z7-20-pcam-5c.xpr
Send the error of the first image and it will immediately open alive but without opening the project.

I opened the XPR project file, first by starting VIVADO and then I took the XPR file, it opens it, however the status of the synthesis and the implementation are Out-of-date following the methodology and at the end, when I export and open SDK it sends me a message as shown in the third image.


Please help!

WhatsApp Image 2021-01-18 at 11.27.19.jpeg

WhatsApp Image 2021-01-18 at 11.34.50.jpeg

WhatsApp Image 2021-01-18 at 11.52.44.jpeg

WhatsApp Image 2021-01-18 at 11.57.47.jpeg

Edited by Marycruz
Link to post
Share on other sites
  • 0

Hi, there!

I'm trying to utilize the pcam to test my convolution module. My plan is adding ip block between AXI4-Stream to Video Out where Video(RGB) data is come from memory(DRAM) and  RGB to DVI Video encoder, just like a picture below.

 

To do so, I need to know the information of video data(RGB). My questions are,

-What is the resolution of the video is?

-What is the frequency of pixclk? 

-How many clock should be counted to stream out 1 row, and how many rows are there for 1 frame?

-How long vsync and hsync becomes 'HIGH' to distinguish each column and row?

-How many VDE signal(at rgb2dvi encoder) is work along sync signal.

 

Since there are too many modules in VHDL and so many application, I cannot write the test bench to find out the information that i'm looking for. 

Could you answer my question, or let me know the way to find out?

 

Thank you, 

 

Have a good day!

image.thumb.png.42daf81ea11ea2829bd2182567ac8db4.png

Edited by Kyle_ISL
Link to post
Share on other sites
  • 0

Hello @Marycruz,
Firstly, I have also encountered the vivado launcher error from time to time. It is nothing serious and can be ignored.
Secondly, Vivado and the SDK can have problems if the paths to the project contain whitespaces
https://www.centennialsoftwaresolutions.com/post/xilinx-sdk-internal-error-the-folder-c-metadata-is-read-only

I would recommend extracting the project in a folder that does not contain whitespace such as "Marycruz_Blas_Hder" or something equivalent.

Best wishes,
Eduard

Link to post
Share on other sites
  • 0

Hello @Kyle_ISL,
Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format.
For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here:
https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf
https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf
https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf

Best wishes,
Eduard

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now