I know there are multiple threads talk about MIG in Arty A7 boards before this new threads. I just hope someone here can help me asnwer my questions.
In my understanding, the A7 board only has 100MHz crystal oscillator while the DDR3L component is designed to run at 667MHz (Require 166.667MHz input clock period)
Question 1) In this case, does it mean i need to use the additional MMCM to generate a 166.667MHz output before feeding the clock into "clk_ref_i" ddr_memory block?
According to the ARTY_MIG_DDR3 resource file, the reference clock and the system clock is configured to the "No Buffer" settings.
Question 2) I believe the reference clock above is referring to the 166.667MHz reference clock input pin? Just need double confirm from you guys.
Question 3) May I know what is the frequency requirement for the system clock --> sys_clk_i? Can i direct connect the 100MHz on-board clock into this system clock?
According to the ARTY_MIG_DDR3 resource file, the system reset --> sys_rst is not defined / No connect.
Question 4) May I know why this reset is not required to bring up the DDR3L in Arty board?
Question 5) Lastly, May i know if the example_top project (Controller + Traffic Generator) that direct generated from the Vivado, can direct used for Arty A7 board? Or it is not so straight forward?
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binry
I know there are multiple threads talk about MIG in Arty A7 boards before this new threads. I just hope someone here can help me asnwer my questions.
In my understanding, the A7 board only has 100MHz crystal oscillator while the DDR3L component is designed to run at 667MHz (Require 166.667MHz input clock period)
Question 1) In this case, does it mean i need to use the additional MMCM to generate a 166.667MHz output before feeding the clock into "clk_ref_i" ddr_memory block?
According to the ARTY_MIG_DDR3 resource file, the reference clock and the system clock is configured to the "No Buffer" settings.
Question 2) I believe the reference clock above is referring to the 166.667MHz reference clock input pin? Just need double confirm from you guys.
Question 3) May I know what is the frequency requirement for the system clock --> sys_clk_i? Can i direct connect the 100MHz on-board clock into this system clock?
According to the ARTY_MIG_DDR3 resource file, the system reset --> sys_rst is not defined / No connect.
Question 4) May I know why this reset is not required to bring up the DDR3L in Arty board?
Question 5) Lastly, May i know if the example_top project (Controller + Traffic Generator) that direct generated from the Vivado, can direct used for Arty A7 board? Or it is not so straight forward?
Thanks,
Binry
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