hdmi port functionality in zybo board

[Guru Prasanth S]

Hi,
IN the link given (https://github.com/Digilent/Zybo-Z7-20-hdmi?_ga=2.136476851.289549728.1571318283-45849474.1563874383), where it demonstrates the functionality of hdmi TX and RX module. Option 5 (start/stop video streaming to video buffer). is not working and the input video is detected by hpd signal. Hence the clarity of functionality is needed. Need the complete functional description of the experiment.

[JColvin]

Hi @Guru Prasanth S,

I am not as familiar with the dvi2rgb and rgb2dvi IP cores that Digilent has developed so I have asked for another engineer more familiar with them for input on this.

Thanks,
JColvin

[Guru Prasanth S]

Up to now all is well. If any issue i will post. Once again Thanks for your support.

[elodg]

So is there anything else that is not working still?

Please mark your post as best answer to let others know what the solution was.

 

[Guru Prasanth S]

Hi,

 I removed debug ILA in the project and generated bit file. It is perfectly working for HDMI source as PC output . Thanks for your cooperation. 

Thanks,

Guru 

[elodg]

There is something wrong with the decoded signals in the ILA screenshots, that I cannot put my finger on and have not seen before. Please activate the debug module in dvi2rgb and screenshot those ILA modules too. The debug signals are documented in https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf.

I do not know what you did in your last post that made it detect the incoming resolution, but seeing the screenshots from earlier I do not trust the console output.

[Guru Prasanth S]

Hi,

Now i am getting the video capture resolution on screen "( When i connected pc hdmi output). I need to know the steps to see the screen of source in display window

I will write the flow used to display from source

->There are three video frames namely 0,1,2

->First I choose 6 ( index 0) then 5 ( Repeated for index 1 and 2)

->Later I choose 6 and then 8 (  i am getting blank image for all index)

Note: 

Test pattern are successfully getting displayed ( for 3 and 4 option for all frame buffers)

 

 

 

 

[Guru Prasanth S]

Hi sorry for long delay,

 I performed experiment for with and without EDID. while spying the signals by chip-scope for (data[23:0], hsync, vsync, data valid,pixel clock )signals  at TX and Rx side.

Following observations are

1. Output of RX side dvi2rgb IP core signals are not matching with the timing reference observed at TX side rbg2 DVI IP input( rgb input driven by Zynq pattern generator).

2. Pixel clock generated by dvi2rgb ip is 148.5 MHz and dynamic clock generator is 148.571 MHz

3. I connected the pc HDMI output as a input to HDMI RX . Still in the window hdmi unplugged is displayed kin teraterm window 

PFA given below the output of Debug ILA for the above two case.

 

 

 

Debug_ila_output_screenshoots.docx

[elodg]

My working theory is that your signal generator does not read/parse the EDID from dvi2rgb and does not realize that the sink only supports DVI. This is documented in https://github.com/Digilent/vivado-library/blob/c79b0d651d750c6fcb52c6b7c58b0837fc27de9b/ip/dvi2rgb/docs/dvi2rgb.pdf and in https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual#hdmi.

Could you try it with a PC with a backward-compatible HDMI output, or a DVI output?

[Guru Prasanth S]

I am happy that you understand my issue correctly.In the mentioned below I answered your questions 

1.What Vivado version are you using?

Ans : Version 2018.2.

2.Are you building the project yourself, or using the https://github.com/Digilent/Zybo-Z7-20-HDMI/releases?

Ans : Yes, I am using the example program, you mentioned in the URL .

3.What is your test setup? Are you using HDMI or DVI sources? What resolutions are they using? What sinks (monitor) are you using?

Ans : -> The video source is PHABRIX SX.

        -> The output of the source is SDI which is converted to HDMI using AJA converter ( Differential clock and data signals).

        -> I tried with formats 1080p60 (3G) and 720p60 (HD) 

       NOTE:

         I changed the preferred resolution in IP 's   accordingly(using UART prompt -teraterm)

        -> Monitor: DELL (3G compatible).

4.Does the monitor ever detect sync and lock to a resolution (even if the image is blank)?

Ans: No.

5.How are you verifying the output of dvi2rgb? ILA? Do you have aPixelClkLckd=1, vde, hsync and vsync pulsing correctly?

Ans: Yes, I verified using ILA  by connecting dvi2rgb and rgb2dvi back to back without Znyq processor . The signals aPixelClkLckd=1, vde, hsync and vsync are pulsing correctly. But, Data is not in correct format ( If I apply red data i am not receiving ff0000),

 

NOTE:

1.HDMI_RX_HPD is high when I connected the sink(Monitor) to HDMI_TX port by connecting dvi2rgb and rgb2dvi back to back.

2.  when I am using the example program, once i choose option 5 (Start/Stop Video stream into Video Framebuffer) and i choose option 7(Grab Video Frame and invert colors)
option 8(Grab Video Frame and scale to Display resolution). i am getting blank display and monitor is not detecting sync and lock to a resolution.

 

 

[elodg]

This thread is a mess, so I will try to summarize it here. @Guru Prasanth S, please correct me, if I understand it wrong.

The Zybo-Z7-20-HDMI demo was tried on a Zybo Z7 -20. Option 5 does not seem to do what is expected, ie. forwarding the input video stream to the output. The console prints HDMI UNPLUGGED even with a video source is connected. Then,  a Vivado-only project was tried with the dvi2rgb and rgb2dvi IPs to test core functionality. Output from dvi2rgb seems to be junk data, and not the expected color pattern.

It is good that the you tried to simplify the test case by instantiating the two IPs yourself. However, there are some caveats you must consider when creating a project from scratch. HDMI_RX_HPD particularly needs to be driven high as documented here: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual#auxiliary_signals.

Please answer the following questions (some of which were asked by James, but remain unanswered):

• What Vivado version are you using?
• Are you building the project yourself, or using the https://github.com/Digilent/Zybo-Z7-20-HDMI/releases?
• What is your test setup? Are you using HDMI or DVI sources? What resolutions are they using? What sinks (monitor) are you using?
• Does the monitor ever detect sync and lock to a resolution (even if the image is blank)?
• How are you verifying the output of dvi2rgb? ILA? Do you have aPixelClkLckd=1, vde, hsync and vsync pulsing correctly?

 

[Guru Prasanth S]

Hi @JColvin, 

       For Previous query( about ip dvi2rgb and rgb2dvi connected back to back).  pls reply As Soon As Possible.

Thanks,

Guru

[Guru Prasanth S]

Hi @JColvin,

I connected dvi2rgb and rgb2dvi IP back to back without any application support and processor to  check the working of those IP's. I observed that dvi2rgb seems to get junk data at the  output of above mentioned when  red data was given as input ( output RGB =FF0000 is expected), I also tested for other data like green and blue . I request you to check the same and reply ASAP. 

[Guru Prasanth S]

The code line 284 and 389 conveys about pixel clock and not associated with video capture 

[JColvin]

Hi @Guru Prasanth S,

My understanding is that the application while using the printf statements occasionally has an issue within that library such that it jumps to a random memory location; this can cause a crash or get the sync process slightly off so that the HDMI is no longer connected. Did you apply the changes I recommended, save the changes, and rebuild the project (through the Project tab -> Build All)? Making these changes made it so I was successfully able to unplug and re-plug the HDMI cables and still have the application successfully re-detect and display on the external monitor.

Thanks,
JColvin

[Guru Prasanth S]

On 11/20/2019 at 10:28 AM, Guru Prasanth S said:

Hi @JColvin,

      I need to know location of  data coming from hdmi rx port that is stored in zynq processor through vdma ip form xilinx  

Hi @JColvin,

                    The teraterm  window (uart prints) is displaying a HDMI UNPLUGGED in video capture resolution when i connect the video source i need to know why is it so??

[JColvin]

Hi @Guru Prasanth S,

I apologize for the delay.

I presume you are using the 2018.2 version of this release? Does the input frame buffer and the output video frame buffer, controlled by options 2 and 6, respectively, on the serial terminal, match values (i.e. both 0, 1, or 2)? If you want to display the test pattern, you will likely need to pause the video stream, and then display one of the two test patterns (options 3 and 4 on the serial terminal) to view it.

The other thing I would recommend changing is two lines of code within the video_demo.c file that is within the Zybo-Z7-20-HDMI project as this will help prevent crashes while the application is running. The two changes are as follows:

In the "DemoPrintMenu" function, change line 284 (on my system anyway, the number may be slightly different for you) as follows:

//LINE 284 currently says:
printf("*Display Pixel Clock Freq. (MHz): %15.3f*\n\r", dispCtrl.pxlFreq);

//Change LINE 284 to instead say:
xil_printf("*Display Pixel Clock Freq. (MHz): %11d.%03d*\n\r", (int)dispCtrl.pxlFreq, (((int)dispCtrl.pxlFreq*1000)%1000));

In the "DemoCRMenu" function, change line 389 (on my system anyway, the number may be slightly different for you) as follows:

//LINE 389 currently says:
printf("*Pixel Clock Freq. (MHz): %23.3f*\n\r", dispCtrl.pxlFreq);

//Change LINE 389 to instead say:
xil_printf("*Display Pixel Clock Freq. (MHz): %11d.%03d*\n\r", (int)dispCtrl.pxlFreq, (((int)dispCtrl.pxlFreq*1000)%1000));

This should help resolve any crashes while running the application.

Please let me know if you have any questions about this.

Thanks,
JColvin

[Guru Prasanth S]

On 11/20/2019 at 10:28 AM, Guru Prasanth S said:

Hi @JColvin,

      I need to know location of  data coming from hdmi rx port that is stored in zynq processor through vdma ip form xilinx  

Hi @JColvin,

                    In the above mentioned i am not getting the screenshot image even i choose option 5 

[Guru Prasanth S]

Just now, Guru Prasanth S said:

Hi @JColvin,

      I need to know location of  data coming from hdmi rx port that is stored in zynq processor through vdma ip form xilinx  

Hi @JColvin,

             Once I chose option 5 i.e start and stop video to buffer. I need to know which option to choose for displaying the frame to desktop.

 

Regards,

Guru Prasanth S

[Guru Prasanth S]

6 hours ago, JColvin said:

Hi @Guru Prasanth S,

The Option 5 on the start/stop video streaming into Video Framebuffer does not turn off the display. It instead no longer sends video frames to the display so that you effectively have a screenshot. This can be more easily seen by having a moving object (such as a mouse pointer) on the display, then pressing the 5 to stop any further frames from being put into the buffer, and then moving the mouse to see that the mouse pointer no longer moves on that display.

Let me know if you have any questions about this.

Thank you,
JColvin

Hi @JColvin,

      I need to know location of  data coming from hdmi rx port that is stored in zynq processor through vdma ip form xilinx  

[JColvin]

Hi @Guru Prasanth S,

The Option 5 on the start/stop video streaming into Video Framebuffer does not turn off the display. It instead no longer sends video frames to the display so that you effectively have a screenshot. This can be more easily seen by having a moving object (such as a mouse pointer) on the display, then pressing the 5 to stop any further frames from being put into the buffer, and then moving the mouse to see that the mouse pointer no longer moves on that display.

Let me know if you have any questions about this.

Thank you,
JColvin