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Vitas tutorial


Sven K

Question

Will there be something like the old 'Getting Started with Vivado IP Integrator' for Xilinx SDK for the new Vitas platform. It would be nice to have something that addresses hardware connection to MicroBlaze. The tutorial in the 'Embedded Software Development' manual only covers sending 'Hello World!' through an UART.

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SHORT STORY FOR HELLO WORLD ON ARTY A7:
(a) Install  Vitis 2019.2 (includes Vivado)
(b) Connect FPGA board via USB and open terminal emulator at 9600 baud
(c) Vivado is used to create the HDL, BD, etc parts of project
(d) Vitis replaces the SDK

VIVADO
(1) Create BD as usual with these adds:
    > MicroBlaze, from IP
    > sys_clock, from board
    > reset, from board
    > usb_uart, from board
(2) Fix "reset": Invert resetn in clk_wiz_0, Output Clocks, Active Low, then reconnect
(3) ... Create HDL Wrapper then Generate Bitstream
(4) File > Export > Export Hardware, with "[x] Include Bitstream"
    Note this generates .XSA, needed in step (9)
(5) Tools > Launch Vitis

VITIS
(6) Select Workspace for Vitis, [Launch]
(7) Create Application Project
(8) Enter a Project name "name", [Next], needed in step (14)
(9) Select "Create a new platform from hardware (XSA)" tab
    Click the blue plus sign
    Select the .XSA file from step (4), [Open], [Next]
(10) Domain, [Next]
(11) Template, Hello World, [Finish]
(12) Right click on "name" from (8) in Vitis Explorer
        Select "Build Project"
(13) Xilinx > Program FPGA
(14) Right click on "name" from (8) in Explorer
        Select "Run As" > "Launch on Hardware ..."
(15) "Hello World" should print to terminal emulator

Vitis.pdf Vivado.pdf

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Hi @Sven K,

I would recommend taking a look at the Nexys 4 DDR (now branded as Nexys A7) Resource Center: https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start where we have a number of tutorials and examples available for Vivado for HDL only projects.

I don't believe we have directly tried working with Microblaze through SDK (now Vitis) specifically, though if you wanted to it would be similar process as done with a Zynq chip (much like in this thread).

Let me know if you have any questions.

Thanks,
JColvin

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