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Duncan.Wu

FMC-HDMI: Dual HDMI Input Expansion Card

Question

Hi sir,

My driver try to access the register content of ADV7611 of the FMC-HDMI card by HDMI1_SDA and HDMI1_SCL.

But there is no Ack from ADV7611 after the second slave address with LSB '1'.

My driver runs on MicroBlaze core Xilinx Kintex Ultrascale KCU105 Evaluation Kit.

Do you have any idea about the symptom?

Thanks

Best regards,

Duncan Wu

2ndSlaveAddress_NoAck.jpg

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Hello,

From the waveform you attached, it seems you are issuing a stop command after the first byte (which is 0xFD), and then you attempt a start command before the second byte (which is 0x99). However, it seems to me that the SDA low pulse during the respective start command is too short, and the corresponding SCL rising edge comes rather late. Therefore, the start condition may not be properly interpreted by the ADV7611. Please see the attached picture for more info (I edited the picture you attached).

I think you should try to correct the Start condition generation, and then try to communicate with the ADV7611 again.

Please let me know if you still see issues afterwards.

Best Regards!

2ndSlaveAddress_NoAck_edited.jpg

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Hi Ionut,

The 0x99 is the slave address 0x98 + 0x1 <- Read.

The 0xFD is the sub address that driver is going to read.

 My read sequence is :

Start --> Slave address (0x98) -> A(S) -> Sub address (0xFD)-> A(s) --> Start --> Slave address with Read bit set (0x99) 

The red marked is observed, and there is also the Start command symptom that you mentioned, but there are Ack from slave device.

I will try to adjust the Timing.

Thank you ~

Edited by Duncan.Wu

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Hi Duncan,

I'm sorry for the delay in answering you.

Yes, you get the Acknowledge from the slave device, but only for the prior transaction(s), for example for the 0xFD byte. For the 0x99 byte, you do not get the Acknowledge anymore. So I would ask the question: do you see a "bad" start condition (like the one from your picture for byte 0x99) for other bytes, before the 0x99 byte? Or is the "bad" start condition only appearing in that one isolated case?

Best Regards!

Edited by Ionut

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Hi Ionut,

Thank you for your information.

I have done a lot of ways to make the good start condition but in vain.

I can only get the good start condition when the SDA/SCL were configured to the PMOD interface of Xilinx KCU105 EVM board.

I can not get the good start condition when the I2C SDA/SCL were configured to the FMC interface pins.

Do you have any idea to fix the bad start condition?

About your question :

I found this issue during the i2c write/read test.

For the i2c write operation, even though there is "bad" start condition, there is ack from the target slave device (ADV7611).

Start --> Slave address (0x98) --> A(S) --> Sub address(0xFD) --> A(S) --> Data --> A(S) --> Stop

So i can only confirm the write command was performed, but still need read back the data of the sub address to double confirm the write was good.  

The sequence below is the Read Command and the first start (mark in red) is a bad start condition, but there is an ack from the slave

Start --> Slave address (0x98) -> A(S) -> Sub address (0xFD)-> A(s) --> Start --> Slave address with Read bit set (0x99).

Please let me know if you have any suggestion about the issue fix.

Thank you ~

Duncan Wu

Edited by Duncan.Wu

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Hi Duncan,

From your description, it seems the "bad" start condition is recognized for some transactions, but not for others. It most likely is marginal all the time, and sometimes the ADV7611 recognizes it correctly, on other times it doesn't.

But it is weird that the problem only occurs when using the FMC interface pins, but not the Pmod pins. It would be interesting to compare the FPGA implementation results between the version using FMC for the I2C lines vs. the one using the Pmod pins:

- Are the two internal circuits the same (I/O buffers, gates, flip-flops)?

- Are the output flip-flop to FPGA pin delays relatively the same between the two implementations?

Also, it would be worth checking, if possible, if there are any significant routing delays on the FPGA board, between the FPGA-to-FMC I2C pins and the FPGA-to-Pmod I2C pins.

Best Regards!

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