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BANK ERROR

Question

I take the following error from VIVADO when I run implemented design

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:  
Output[0] (LVCMOS18, requiring VCCO=1.800) and Output[1] (LVCMOS33, requiring VCCO=3.300)
 

My constraints code is like that

#Switches 

#First 4-Bit Binary Number
set_property PACKAGE_PIN W15 [get_ports I4]
    set_property IOSTANDARD LVCMOS33 [get_ports I4]
set_property PACKAGE_PIN V15 [get_ports I5]
    set_property IOSTANDARD LVCMOS33 [get_ports I5]
set_property PACKAGE_PIN W14 [get_ports I6]
    set_property IOSTANDARD LVCMOS33 [get_ports I6]
set_property PACKAGE_PIN W13 [get_ports I7]
    set_property IOSTANDARD LVCMOS33 [get_ports I7]

#Second 4-Bit Binary Number
set_property PACKAGE_PIN V17 [get_ports I0]
    set_property IOSTANDARD LVCMOS33 [get_ports I0]
set_property PACKAGE_PIN V16 [get_ports I1]
    set_property IOSTANDARD LVCMOS33 [get_ports I1]
set_property PACKAGE_PIN W16 [get_ports I2]
    set_property IOSTANDARD LVCMOS33 [get_ports I2]
set_property PACKAGE_PIN W17 [get_ports I3]
    set_property IOSTANDARD LVCMOS33 [get_ports I3]
    
#LEDs
set_property PACKAGE_PIN L1 [get_ports {Output[0]}]
    set_property IOSTANDARD LVCMOS33 [get_ports{ Output[0]}]
set_property PACKAGE_PIN P1 [get_ports {Output[1]}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Output[1]}]
set_property PACKAGE_PIN N3 [get_ports {Output[2]}]
    set_property IOSTANDARD LVCMOS33 [get_ports{ Output[2]}]
set_property PACKAGE_PIN P3 [get_ports {Output[3]}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Output[3]}]
set_property PACKAGE_PIN U3 [get_ports {Output[4]}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Output[4]}]
    
#Function Select 
set_property PACKAGE_PIN V2 [get_ports Selectt]
    set_property IOSTANDARD LVCMOS33 [get_ports Selectt]

 

Can someone tell me where is the mistake or how can I fix the error?

Note: Implementation works properly without constraints 

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