Old Spartan 3 UART code to Digilent CMOD S6 not working

[Bryan_S]

The company I work for has several old Digilent Spartan 3 development boards that are still being used in some custom test equipment. I am tasked with finding a suitable replacement development board to create more of the same test equipment. The old Spartan 3 boards are no longer available. I chose the CMOD S6 which meets the requirements as a replacement. I have to tried to port over the old code to the new CMOD S6 board. The operation of the FPGA is to receive serial data from a Pic Microcontroller which is receiving RS232 data from software running on a computer. The computer basically sends ASCII data to the PIC that then in turn sends  serial data to the FPGA telling it to turn on one of 42 relays in the equipment. I have plenty of programming experience in Pic Microcontrollers, Arduinos, and ARM processors, as well as computer software such as LabVIEW and more. I have very little experience in VHDL and FPGAs. The issue I am having is I ported over the code to the CMOD S6, programming both the FPGA and Flash device in Xilinx ISE and Impact. The UART receive is not working on the FPGA. I modified the constraints to work with the CMOD S6 assigning  ports to their proper pins. I don't think I have the timing correct (clock) that is used for the Baud generator mainly because I just don't have a good understanding of the clock the FPGA uses. I don't have the code with me right now as I'm at home. The question I have is the code uses clk16x as the source of the timing for the baud generator. The clock on the CMOD S6 is 8mhz. Does that mean clk16x ( which is clk16x : IN std_logic) is also at 8Mhz?  Do I need to somehow define how clk16x gets it's timing or clock from? Maybe in timing constraints? Originally the clock on the old Spartan board was 50Mhz and the Baud generator used that for calculating the baud rate. Now I working with an system clock of 8Mhz. There is a way to create a 50mhz clock for the baud generator  but I'm not sure how to do that yet and have it go to clk16x input. Help would be greatly appreciated.  I'll attach the code later if needed.

[Ana-Maria Balas]

Hello @Bryan_S,

Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start.

I looked into the source files and there is clk_gen_50MHz.vhd.

You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used.

I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock.

But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd.

I don't know if you'll use the sources from above, but I hope it helps.

Best regards,

Ana-Maria Balas

 

[Bryan_S]

Thank you for your help.  I guess when I mentioned "clk16x" it is just arbitrary identifier for a clock input. Could have maybe just use "Clk" instead. This was not my code or work. That person who wrote it is no longer working at this company. Seeing I'm now the hardware and software programmer for them I have to get this code to work on a different FPGA now. I uploaded my project files if you interested in looking at them. I'll get this figured out eventually I think , or hope...  

UART_Project.zip

[zygot]

1 hour ago, Bryan_S said:

I'll get this figured out eventually I think , or hope... 

Sometimes people mistakenly try to create a derived baud rate clock that closely matches the baud rate. UARTs should be able to accommodate a significant variation of baud rate error, perhaps 15% or so. So a better way to think of it, particularly on the receive side is creating lots of samples and keeping data transitions near the middle of a baud's worth of sample units. This means that clocking the UART entity at a high clock rate, providing a lot of samples per baud period, will be optimal.  A 50 MHz clock for 115200 baud is fine but I've been using a 100 MHz clock for 921600 baud that's reliable.

Don't think or hope... simulate, simulate.. and simulate some more. The first thing that I'd do if made custodian for someone else's code would be to simulate everything until I understood it. Reading source text often not sufficient and commentary is rarely accurate. There are a number of UART based projects in the Digilent Project Vault, some with testbench HDL tha might be helpful. 

[Ana-Maria Balas]

Hi @Bryan_S,

We don't have the necessary resources to investigate/correct the code of your project.

However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need.

Cheers,

Ana-Maria

[Bryan_S]

Thanks, Ana-Maria, the UART_RX_CTRL.vhd helped as I have it functioning now as needed. I didn't need to implement the 50Mhz clock but will try an add that later possibly. FPGA's are quite different then what I'm use to working with. Still don't have a full understanding of VHDL either, but I think I did pretty good for only working a week on it. You help was greatly appreciated, as well as the others who replied.

[Ana-Maria Balas]

I'm glad you worked it out!

Best regards,

Ana-Maria