Arty S7 Board Layout

[ykaiwar]

Hello,

I am working on a project in which we've mirrored the DDR portion of the Arty S7 schematic on a new PCB design. We recently received the boards and the DDR does not appear to be working. I can load in a test .bit file into the Arty S7 dev board I've purchased but it doesn't load into the electronics I designed. I've checked the schematic multiple times and it matches the Arty S7 schematic, so I'm pretty positive that something is incorrect in my layout. Can you provide the layout of the Arty S7 board so I can compare the two? If not the entire layout file, just the DDR portion would be helpful, or anything that points me in the right direction. 

Thank you,

Yash

[D@n]

@ykaiwar,

It sounds like there's an issue with the DDR3 SDRAM on your new board, but you've declared an issue with the ability to configure the FPGA at all.  So let me ask about some basic things in between configuring an FPGA and getting the DDR3 SDRAM working:

1. Can you turn an LED on?
2. Can you turn it off?  Can you make it blink?
3. Can you mirror the serial port (you do have one, right) from receive back to transmit and verify that it works?

If these tests fail, then you aren't yet ready to discuss possible SDRAM problems.  If they succeed, then you can start to bootstrap your FPGA's capability more and more until you know exactly what is and isn't working.

Dan

[asmi]

When it comes to DDR3, the layout is a make or break factor. Did you do length matching as described in MIG user guide, and used controlled impedance traces as required? If not - it will never work no matter what you do. DDR3 has a fair bit of robustness built into it, and Spartan-7/Artix-7 can only drive it at mere 333/400 MHz (depending on speed grade and if you use DDR3L voltage levels or regular DDR3 ones), which is very slow for DDR3, but it doesn't mean that it will accept any random layout. From my experience, impedance is not very important at such slow speeds - especially if you have address/control terminations, but trace length matching still is.

Finally I seriously doubt Digilent will give you the layout - they seem to believe is security by obscurity too much. So if you haven't done so - go and RTFM MIG user guide until you understand what exactly needs to be done in order to successfully implement DDR3(L). It's not very complicated, but attention to details is paramount.