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Tejna

Petalinux Build fail: Arty S7-50 (using Petalinux Support for Digilent Boards README)

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Hi,

I am working on Petalinux to get it running on Arty S7-50 Digilent Board, and am following the Petalinux Support for Digilent Boards README. I am currently using Petalinux 2017.2 installer and Ubuntu 16.04.1 LTS (Dual boot Ubuntu and Windows). I have successfully installed Petalinux and have completed all the steps mentioned in README until Build the petalinux project. The petalinux-config --oldconfig command was successful but when I run the petalinux-build command I am getting the following errors listed in the attached screenshot.

I have tried looking up the same online, but did not get the clarity on what is causing the error or how I can rectify it — from the line below I see that it is trying to access a folder named "mitchellorsucci" which does not exist on the PC. I am new to petalinux, any idea on where I could be going wrong would be highly helpful.

PermissionError: [Errno 13] Permission denied: '/home/mitchellorsucci'
ls: cannot access '/home/mitchellorsucci/artys/Petalinux-Arty-S7-50/Arty-S7-50/build/tmp/log/cooker/plnx_microblaze': No such file or directory


Thank you,
Tejna

config success.png

build fail.png

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16 answers to this question

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Hello,

Since you mentioned that you successfully built the mcs file you can choose an alternate way to program the flash. Instead of using the SDK (the recommended way in the mentioned readme), let's use Vivado.

Please open Vivado, do not open a project. In the the welcome screen please open Tasks/Hardware manager. Then Open Target / Autoconnect, you should see your FPGA in the Hardware tree. Right click on FPGA, select "Add Configuration Memory device ...". Select s25fl128sxxxxxx0-spi-x1_x2_x4.

Then right click on the flash device you just added in the Hardware tree, select "Program Configuration Memory Device ..." and select your mcs file to be programmed.

 image.thumb.png.6113548266a132f81d73e3b0a0ee9bb8.png

Please note that the board used for this caption uses a different FPGA.

On the other hand, if you want to address the errors you mentioned in your previous post, most probably you lack the (HDL) top wrapper. Please right click on system.bd, select "Create HDL wrapper ..." and then rebuild.

Good luck.

Edited by Cristian.Fatu

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Thanks for reporting. There was a problem with the project.

We updated the project and the instructions in the README.

Just run the following commands:

git clone https://github.com/Digilent/Petalinux-Arty-S7-50.git
cd Petalinux-Arty-S7-50/Arty-S7-50/
git submodule update --init
petalinux-config
petalinux-build

 

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Thank you so much for updating the project. I am now successfully able to build and create the boot.mcs file.

Now that the .mcs file is created and I have to program the flash on Arty-S7, I am facing issues while trying to load the image using the Xilinx tools->Program Flash feature as mentioned in the README document. I have attached a screenshot of the pop-up error message I am receiving when I try to do the above. I am guessing this is because we first need to open our existing project in Vivado and export the hardware to SDK, before programming the flash. However I am unable to find the .xpr file in the project folder that I have cloned from github, in order to open it in Vivado.

Could you please suggest me where I can find the .xpr file or how I could proceed from this step in order to be able to use the Program Flash feature of Xilinx SDK.

Thank you so much,
Tejna

sdk.png

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Hello,

You are getting this message because you must have an open workspace in SDK. This wortkspace should contain a hardware platform that is needed in this operation. 

This is specified in the readme file you linked in the initial posts:

Quote

After exporting your hardware (HDF) from Vivado and launching SDK with the ./sdk folder as your workspace, do the following: <...>

 Please write us if you still encounter problems.

Good luck.

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Hi,

I am having trouble getting the project to open up in Vivado. I am aware how to export the hardware from Vivado to SDK, but in order to do that I was not able to open the project in Vivado. I tried looking for the .xpr file within the Petalinux-Arty-S7-50 project, but was unsuccessful in finding it. I have attached a screenshot of an example program that I had worked on previously, here I was using the myAdder.xpr file to open the pre-existing project (just an example to show the .xpr file). 

I am not able to find such a .xpr file for the Petalinux-Arty-S7-50 project (illustrated in the attached screenshot below). I have checked all the subfolders within the project — any help on how I can open the Petalinux-Arty-S7-50 project in Vivado would be highly helpful.

Thank You,
Tejna

open_proj.PNG

Petalinux_open.PNG

Edited by Tejna

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You are right, there is no xpr file provided in the git repository.

In order to build the Vivado project  you must use the proj/create_project.tcl script to create it. Please open Vivado and follow these steps In the tcl console (at the bottom of the screen):

cd to the proj directory of the folder structure. 

run: source ./create_project.tcl

Please write if you still encounter problems.

 

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I am getting the following error when I try the tcl command source ./create_project.tcl (shown in the screenshot below). When I look into other Digilent github demo projects folders, I am able to find the create_project.tcl file within the proj folder. But this is not available for the Petalinux-Arty-S7-50 project (screenshot attached below). I have tried to look for this as suggested in the Using Digilent Github Demo Projects and How to Generate a Project from Digilent's Github Repository (Legacy) articles but was not able to find the required tcl script file (create_project.tcl) within the Petalinux-Arty-S7-50 project folder. Please let me know how I can go about this issue.

Thank You,
Tejna

tcl.png

pmod_proj.png

petalinux.png

petalinux_folder_path.png

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Hi,

Thank you so much for the above clarification.

Now I am able to successfully open the project in Vivado, but getting the following error as mentioned below (screenshot attached):

[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_PWM_0_0

Initially I was trying the project with the Vivado WebPACK edition, I got the same error mentioned above. Since Digilent recommends using the Vivado Design edition, I guessed maybe that was what was causing the error (because of the edition mismatch — project was built using Vivado Design). I uninstalled the WebPACK and have installed Vivado Design edition. I am using Vivado 2017.2, same as the one mentioned in the README. I tried the whole procedure again with Vivado Design edition (2017.2) but still no luck — The same error is popping up. Please let me know how I can rectify this.

Thank you,
Tejna

error.png

tcl console.png

Edited by Tejna

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Hi,

Thank you very much for the alternative approach to program the flash. I am now able to successfully boot Petalinux onto the Arty-S7 development board.

Really appreciate all the help I have gotten through this forum in getting this to work.

Thank you so much again!
Tejna

P.S: Just to mention, I did try the first approach again by trying to create a HDL wrapper as mentioned above, but was getting an error (illustrated in the attached screenshot)

boot_successful.png

wrapper_error.png

Edited by Tejna

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You are welcome, we are happy that the flash is programmed.

Unfortunately this project seems to be marked as having internal use. And maybe this is the reason you get so many problems, as the documentation is not detailed enough.

 

Edited by Cristian.Fatu

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Hello @Tejna,

 

First, you have to reset output products for your block design. After that, you have to generate output products. You need to go to your source window, right click on block design, select output products, and generate output products.

 

Best Regards,

Bogdan Vanca 

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Hi @BogdanVanca,

I am not able to choose reset output products or generate output products — they are both greyed out (illustrated in the attachment below).

Best Regards,
Tejna

output products.png

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Hello @Tejna,

Please try running the fallowing tcl command: set_property IS_LOCKED false [get_files "your xci files for the PWM ip".xci]. After that, try to reset output products and generate output products. 

Best Regards,

Bogdan Vanca

 

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