• 0
ekazemi

dynamic phase configuration on arty s7

Question

Hi all,

I am struggling with a part of my project and I am trying to generate a clock with my FPGA ( to provide an external clock for another processor) and I want to reconfigure its phase by setting an input or sending variables by UART. I have read the XAPP888 (v1.8) and I could not undrestand if i can do it through clock management interface of my vivado or should i integrate new ip (DRP) ? Does any one have this experience?

 

Thank you in advance

Share this post


Link to post
Share on other sites

5 answers to this question

Recommended Posts

  • 0

@ekazemi

What frequency rates are you trying to achieve?  This method will get you user-controlled phase to within about 1ns or so, and it works nicely for sending something off-chip.

But to your question, I have yet to try the dynamic interface of any clock management hard-cores.  I've looked them over a couple of times, but ... not actually tried any.

Dan

Share this post


Link to post
Share on other sites
  • 0
13 minutes ago, D@n said:

@ekazemi

What frequency rates are you trying to achieve?  This method will get you user-controlled phase to within about 1ns or so, and it works nicely for sending something off-chip.

But to your question, I have yet to try the dynamic interface of any clock management hard-cores.  I've looked them over a couple of times, but ... not actually tried any.

Dan

I am trying to generate 16 MHz clock. by using MMCM i generated two signal with different phases. then by combining them ( in my vhdl code) i generated a glitch in my output clock. now I want to configure this glitch ( I should have a control over phases to reconfigure the glitch parameters) . 

Share this post


Link to post
Share on other sites
  • 0

If you are trying to create clock "glitches", then you definitely want to avoid using the MMCM.

Try the above linked method.  I think you'll find no problems at rates as slow as 16MHz.

Dan

Share this post


Link to post
Share on other sites
  • 0

@ekazemi,

The code I presented has user-selectable phase resolution, subject to the accuracy of the originating clock and some quantization error on the output.  This can easily be adjusted to create whatever phase clock signal you want.  Be aware, as with everything FPGA, the devil is in the details.  For example, if you aren't careful, you could create a glitchy clock without intending to.  On the other hand, the technique is simple enough as to offer lots of possibilities--which sounds just like what you are looking for.

Dan

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now