I am struggling with a part of my project and I am trying to generate a clock with my FPGA ( to provide an external clock for another processor) and I want to reconfigure its phase by setting an input or sending variables by UART. I have read the XAPP888 (v1.8) and I could not undrestand if i can do it through clock management interface of my vivado or should i integrate new ip (DRP) ? Does any one have this experience?
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ekazemi
Hi all,
I am struggling with a part of my project and I am trying to generate a clock with my FPGA ( to provide an external clock for another processor) and I want to reconfigure its phase by setting an input or sending variables by UART. I have read the XAPP888 (v1.8) and I could not undrestand if i can do it through clock management interface of my vivado or should i integrate new ip (DRP) ? Does any one have this experience?
Thank you in advance
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