ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)'

[josina]

Hello,

I am trying to bring up Cortex M0 on Arty-A7 FPGA board from Digilent. I have installed the digilent board files at C:\Xilinx\Vivado\2019.1\data\boards\board_files. I use Vivado 19.1 and 18.3 version. IN both version, I get the following error,

ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.
ERROR: [IP_Flow 19-3439] Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
::xilinx.com_ip_proc_sys_reset_5.0::post_propagate Line 23
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
ERROR: [BD 41-241] Message from IP propagation TCL of /Clocks_and_Resets/proc_sys_reset_base: set_property error: Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - Custom
Customization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.
Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.

Please help me understand this error and how to go fix it/or go around it. 

 

[JColvin]

Hi @josina,

Those of us here at Digilent have not developed any of the Cortex cores with the Digilent boards; any work that exists has been done by Xilinx and ARM. Additionally, I do not think the Cortex M0 has been implemented on an Artix 7, or at least this publication from Xilinx only shows the Cortex M1 and Cortex M3 has been implemented on Digilent boards. I did find some materials working with the Arm M1 and M3 here and here that I would recommend taking a look at.

Otherwise, I would recommend asking on the Xilinx forum how you might get the Cortex M0 implemented on an Artix 7 chip.

Thanks,
JColvin