Interfacing PMOD in Vivado

[krusing]

I'm really new to this all, so apologies. I couldn't find a simple answer to my question about the PMOD connectors (specifically the standard PMOD JE) on the ZYBO.

I have, for example, an 8 bit counter in VHDL. I want to output these 8 bits to JE. It's all very simple, but I'm not sure how to start. I've read tutorials which go far more complex than I want to right now. I've tried creating an IP block out of VHDL code, and I've also tried just adding the "Binary Counter" IP block.

1. How do I get a clock signal to input to the counter? I tried adding an IP called "Clocking Wizard," and running the Connection Automation. Then I get errors about being unable to place reset_rtl, which was an input created by the Connection Automation.

2. Is there a tutorial that I've missed somewhere, which outlines creating a simple design and outputting something on the PMOD pins?

[snohomish77]

Not sure if this will help but I had a similar question that I posted on 4 April titled "Getting pmod ports into a block diagram"

It was answered by Andrew Holzer on 7 April.  He referred me to some files to download, which I did and it got me going again.

You did not miss any tutorial that I know if.

Hope this helps.

Snohomish

[krusing]

On 4/14/2016 at 11:24 PM, snohomish77 said:

Not sure if this will help but I had a similar question that I posted on 4 April titled "Getting pmod ports into a block diagram"

It was answered by Andrew Holzer on 7 April.  He referred me to some files to download, which I did and it got me going again.

You did not miss any tutorial that I know if.

Hope this helps.

Snohomish

Thanks Snohomish,

I took a look at that post, but the interface to those parts seemed to be AXI4, which I don't understand that well.

 

After some trial and a lot of error, I found out that you can remove the RESET pin on the Clocking Wizard, and use the sys_clock as an input. Then I just had to fix the port I was using as an output for the counter, then assign that port to JE in the .XDC file.

[artvvb]

Krusing,

It sounds like you are doing things the right way, for pins that are available in the board file, drag the name into your block design and use *run connection automation*. For others, use *right click* -> *create port*, with the same name as you use in the XDC file. Getting a clock of a useful frequency is slightly harder, the approach I'd take would be to use two of Xilinx's binary counter IP. The extra counter module can divide the clock, using its threshold output as the clock enable of your original counter. Enabling the *restrict count* and *sync threshold output* options in this new counter would let you control the frequency at which the original counter updates, by only letting it increment every so often. I'll attach an image of a quick and dirty block design for this - I'm using the LEDs instead of JE, but the principle is the same. I have the design incrementing the LEDs at 8Hz, by setting the count restrict and sync threshold appropriately for the frequency being created by the clocking wizard (100MHz / 8Hz = 0xBEBC20, using that minus one, for a 24 bit counter). I'm not sure what frequency you are targeting on the PMOD port, but anything lower than around 5MHz will require something like this. Adding a reset to the counter should be as simple as enabling the SCLR pin in each counter IP, and connecting it to the XDC file's reset pin - as far as I am aware, the ZYBO's board file reset has some issues right now.

The AXI interface is for connecting your custom logic to the processor side of the ZYBO, and since it sounds like you are trying to use only the FPGA side for this project, should be unnecessary.

Thanks,

Arthur.

 

Edit: To be clear, all the ports in this image were created with create port and the master XDC, rather than the board file.

 

[krusing]

21 hours ago, artvvb said:

Adding a reset to the counter should be as simple as enabling the SCLR pin in each counter IP, and connecting it to the XDC file's reset pin - as far as I am aware, the ZYBO's board file reset has some issues right now.

Thank you, that clears up the issues I was having.

 

21 hours ago, artvvb said:

The AXI interface is for connecting your custom logic to the processor side of the ZYBO, and since it sounds like you are trying to use only the FPGA side for this project, should be unnecessary.

Understood. I appreciate you taking the time to clear that up for me.