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@Ahmed Alfadhel,

Perhaps the most complete tutorial out there is asic-world's tutorial.  You might also find it the most vacuous, since although it tells you all the details of the language it doesn't really give you the practice or the tools to move forward from there.  There's also a litexsoc (IIRC) by enjoy-digital that I've heard about, but never looked into

An alternative might be my own tutorial.  Admittedly, it's only a beginner's tutorial.  It'll only get you from blinky to a serial port with an attached FIFO.  That said, it does go over a lot of FPGA Verilog design practice and principles.  It also integrates learning how to use a simulator, in this case Verilator, and a formal verification tool, such as SymbiYosys, into your design process so that you can start learning how to build designs that work the first time they meet hardware.

I'm also in the process of working to prepare an intermediate tutorial.  For now, if you are interested, you'd need to find most of the information that would be in such a tutorial on my blog.  (It's not all there ... yet, although there are articles on how to create AXI peripherals ..)

Feel free to check it out.  Let me know what you think,

Dan

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I haven't bought a textbook for quite a few years now so I don't have any suggestions. There are a lot of levels to learning an HDL. One is the language syntax and basic concepts of timing, concurrency and other aspects of simulating a model. Then there is the usage of languages like VHDL and Verilog for synthesis. Both are central aspects of designing logic in programmable devices. I can't emphasize enough how important learning basic digital design concepts is to developing competency in FPGA design regardless of your source preferences. I doubt that there is a good text that covers all of these facets. Unless there is a University nearby finding a place to browse though books to see if they might be worth the investment is a difficult proposition these days.

I know that @D@nloves verilator. He's the only one concentrating on programmable logic design that I know of who uses it. Be aware that it is a cycle based simulator. These tend to be a lot faster than regular logic simulators and certainly have a place. Don't be afraid of the simulator tools widely used in industry where products are programmable logic based. The native Vivado simulator and ModelSim provided by Intel are preferred simulation tools for programmable logic. These are time based simulations that can simulate in units of picoseconds if that's warranted. They also use compiled libraries that understand the vendors device architecture. Best of all they can do post route timing simulations. Learn how to write good testbenches that work with the vendors simulators. Part of the design process is being able to conceptualize real world device behavior; the less idealistic the more complete your design process and logic will be.

Edited by zygot

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On 10/13/2019 at 9:45 PM, D@n said:

formal verification tool, such as SymbiYosys, into your design process so that you can start learning how to build designs that work the first time they meet hardware

This line keeps popping up in my thinking because it's been bothering me; not because it's necessarily wrong but because it suggests ideas that are.

Engineers and scientists work with models in order to interact with or manipulate reality. Idealistic, simplistic, and incomplete models get you so far. The better your model the more likely that you will be able to maintain the illusion that you have conquered some aspect of reality.

There are a lot of reasons why programmable logic that connects an FPGA to an external device fails to work. Without attempting to be all inclusive I can think of a number of reasons off hand:

  • The logic, that is the behavorial boolean mathematical design is flawed
  • The model of the external device behavior is conceptually wrong or simplistic
  • The final implementation has timing errors; which basically amounts to a failure to implement a design so that it operates correctly
  • The physical interface between the FPGA and the external device is poorly conditioned.

Any sales pitch for a product that claims to solve all of those problems mentioned above should be treated with considerable scepticism. A formal logic analysis tool can certainly help find incomplete or in some cases faulty logic. The usual suspects are if-then-else and case statements that don't include all possible logic input conditions. Formal logic analysis tools can't over come deficient models of how the external device works, or how the interface works, or all of the conditions your design needs to account for. They certainly don't provide perfect models for anything.

At some point for a given programmable logic device and a clock rate the timing and perhaps placement constraints start becoming as important to success as the actual HDL code. And, depending on your synthesis and implementation settings it's a bad assumption that the optimized synthesized and implemented logic agrees with what the HDL designer intended for the tools to infer. You also need a good oscilloscope and the skill to use it in order to "close the loop" as it were for a lot of interface designs.

There are a lot of tools available for the FPGA designer. The competent developer will be familiar and expert enough with all of them to understand the tool limits and strengths. The best tool lies somewhere between the designer's ears. Don't rely on software based tools to make up for your lack of expertise or inability to develop models that are adequate for the job at hand. Use all of the tools, as is appropriate, to make the one you walk around with a better tool.

Edited by zygot

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Hi @D@n,

On 10/14/2019 at 4:45 AM, D@n said:

Feel free to check it out.  Let me know what you think,

After I did my check on the different Verilog tutorials, I would like to inform you that your Verilog tutorails on zipcpu.com is the best suited for me. Since they are more tidy and also fill the gaps in other tutorials. Such as in your tutorial lsn-01, Verilog literals are discussed. 

But, I will not use Verilator , since it lacks to its own GUI and hard to carry out a regular test bench with it. I will use Vivado Simulator since I have an experience with it (I used it to make test benches by VHDL) and I haven't any issue with it. 

Thanks 

Edited by Ahmed Alfadhel

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