PMOD CLS High Speed PMOD spike on SS

[Tim S.]

I am using the PMOD CLS to develop a custom CLS driver via the SPI interface. The PMOD CLS data sheet did not define the protocol, so I used the Analog Discovery 2 to watch the SPI traffic of the Digilent PMOD CLS driver in a Microblaze architecture on a Arty A7-100T board. The FPGA signals are SS, MOSI, MISO, SCK.

For my design, MISO is an input that is optimized away for lack of logic connection. The SS, SCK, and MOSI are operated the same as the C api calls from the PMOD CLS BSP driver. With the Digilent driver, I can control the two lines of text to display any text. With my own driver, I believe the only issue is that their are several nanosecond duration spikes on the SS signal during a data transfer. This interferes with the escaped commands ESC]digit;digitdigitCMD as well as the text data. The spikes appear random: SS is held low and for nanoseconds the SS may rise to a value of '1'. Note that I am driving the PMOD CLS via JB of the Arty A7-100T. The jack JB is a high-performance port. I am running the SCK at 625 kHz.

Has anyone seen spikes like this before on the SS and found a solution? Thanks.

 

[zygot]

1 hour ago, Tim S. said:

ack JB is a high-performance port

By "high performance" I assume that you mean differential PMOD.

Usually, unwanted "spikes" or signal transitions are due to driver contention or termination and or impedance issues. If there's only one driver on a signal then that eliminates contention.

A possibility is that if you are using differential signals pairs as two single-ended signals, and the traces are laid out as true differential, then you will have coupling of the two signals. This will be noticeable when either one transitions from one state to the other. It may or may not cause the interface to fail. One way round this is to make sure that either the _n or _p trace is always static, high or low whenever transitions on the other are important. For (most) practical use case scenarios the differential PMOD is a 4-pin interface. Sometimes you can come up with a way around this but not always.  

[edit] For the sake of completeness I should point out the possibility that your logic isn't doing what you think it is. This problem is readily resolved with the Vivado simulator and a good testbench.

[zygot]

I can remember when PMOD meant 6-pin connector. I still have boards with 6-pin PMOD connectors. At some point Digilent realized that 4 signals was very limiting to the usefulness of the PMOD and got the idea of putting 2 PMODs side by side to create the 12 pin PMOD that most people are familiar with today. I wager that there is no person on the planet who can come up with an explanation as to why in the intervening 20 years or so no one at Digilent hasn't realized how limiting the 12-pin PMOD is for modern usages of FPGA development boards, both for customers and Digilent engineers. It certainly isn't due to a lack of effort and cajoling on my part. And yet I get emails from them telling me that my opinions are important and they want me to fill out a survey...

Digilent marketing need only spend as much time reading their forums as I do to figure out what's obvious to the rest of us. Come on now, we've been in the 21st century for a while now; in which century should your company operate?