Question

I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). 

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Thank you!

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14 hours ago, J_Long said:

Will swapping them damage any components or just not work?

The answers to your questions are to be found by continuing to follow the signal names back to the FPGA IO Bank on the schematic and then consulting the Xilinx Series7 Select IO User Guide ( or the appropriate IO User Guide for other families )..

If the IO Bank for a pin is powered by the appropriate Vcco and the Xilinx pin name has a _n or _p suffix then it and it's partner can be used as an LVDS differential signal pair. Swapping _p/_n signals for as LVDS pair simply inverts the signal similar to the boolean not function. If the IO Bank Vcco is 3.3V there is one differential IOSTANDARD that can be used if the proper termination is provided. All of the possible IOSTANDARD possibilities for a given Vcco are in the Xilinx Series 7 Select IO User Guide. Anyone connecting a circuit to an FPGA pin is responsible for understanding the Xilinx documentation for a particular device.

Pins that are differential capable are can also be used as single-ended logic. There's another document that defines Xilinx pin naming conventions. All of this useful information and more is freely available to every Vivado user who takes advantage of the Document Navigator application that is installed with the tools. Read the documentation, then impress your family and friends, win trivia contests and use your FPGA safely and effectively.

Edited by zygot

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