How to create a custom AXI Pmod IP without constraint file

[krjdev]

Hello,

 

I want create a custom IP for the Pmod interface. A simple GPIO Interface as example.

But I run into a problem.

 

I have downloaded the vivado-library from Digilent and placed the interface folder in my project.

The Pmod Interface is available under Vivado. I added these port definitions in the top VHDL file of the AXI peripheral:

pmod_pin0_i     : in std_logic;
pmod_pin0_o     : out std_logic;
pmod_pin0_t     : out std_logic;
        
pmod_pin1_i     : in std_logic;
pmod_pin1_o     : out std_logic;
pmod_pin1_t     : out std_logic;
        
pmod_pin2_i     : in std_logic;
pmod_pin2_o     : out std_logic;
pmod_pin2_t     : out std_logic;
        
pmod_pin3_i     : in std_logic;
pmod_pin3_o     : out std_logic;
pmod_pin3_t     : out std_logic;
        
pmod_pin4_i     : in std_logic;
pmod_pin4_o     : out std_logic;
pmod_pin4_t     : out std_logic;
        
pmod_pin5_i     : in std_logic;
pmod_pin5_o     : out std_logic;
pmod_pin5_t     : out std_logic;
        
pmod_pin6_i     : in std_logic;
pmod_pin6_o     : out std_logic;
pmod_pin6_t     : out std_logic;
        
pmod_pin7_i     : in std_logic;
pmod_pin7_o     : out std_logic;
pmod_pin7_t     : out std_logic;

 

After that I selected Ports and Interfaces in Package IP window.

Then I add a Pmod Interface and mapped the ports from the VHDL file with the Digilent Pmod Interface.

I added Pmod to the description field.

But when I repackage the IP and  I try to click on Connect Board Component it doesn't work.

 

What is missing?

 

Thanks in advance!

[artvvb]

Hi @krjdev

The "Connect Board Component" flow requires modifications at least to the generated xgui.tcl, and to the parameters of the Pmod interface port, within the IP. You can see how we added board file support in the existing IPs.

Internally, we typically create new Pmod IPs by modifying an existing one that is known to be good. You can also connect custom IP to the interfaces of the Pmod Bridge, but this will likely not be doable through connection automation.

Thanks,

Arthur

[krjdev]

Hi @artvvb

 

Okay, thanks.

 

I have added these parameters. Now the "Connect board component" works.

 

But I run into a new problem.

I have created a unmanaged XDC (TCL) file for the IP.

When I open the Top Level Design and execute the following TCL commands by hand, it works:

synth_design
source path/to/my_unmanaged_constraint.tcl
opt_design
place_design
route_design
write_bitstream

But not in GUI. Vivado doesn't execute the file.

I don't know how the set the properties from the file to get executed. Tried the following:

Parameter: USED_IN_IMPLEMENTATION

Process Order: EARLY

[artvvb]

We've used XIT scripts to apply additional constraints. Example from the PmodAD5, which handles hooking the IP's interface to the board file interface. I've pasted the contents of the "xitscript.tcl" script we use to add this file to the IP packager below:

set imp_fg [ipx::add_file_group -type {xilinx_implementation} xilinx_implementation [ipx::current_core]]
ipx::add_file {utils/board/board.xit} $imp_fg
set_property type {{xit}} [ipx::get_file utils/board/board.xit $imp_fg]
set_property used_in {{implementation} {board}} [ipx::get_file utils/board/board.xit $imp_fg]

-Arthur