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*.xdc file upload (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D)


I own an Digilent Avnet Zedboard (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D). This is an older version of the zedboard.    Can anyone upload the master *.XDC file for this specific board? I looked at the master *.XDC files available at this website and I believe that it is incompatible with my specific development kit.   Is Silica Avnet, Xilinx, or Digilent, supposed to make this file available to the public.   I checked the website, GitHub, however, it appears that the file is missing.

The correct file should match, (or be very similar to),  the file made reference to on page 34 of the Silica Avnet Vivado tutorial that I have attached.


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Hi @Zed_Guy,

The ZedBoard XDC file is available on out GitHub here: https://github.com/Digilent/digilent-xdc/

I looked in your document and I saw that they changed the name of the ports in the XDC to match with their projects. You can either use in the project, the names used in the XDC or change in the XDC the names according to your project. By the fact that they are using "my_constraints.xdc" implies that they created a XDC file specific for the project in the guide, and probably used just what they needed. 

Normally, where you found the project and the guide, you should've been able to find the that XDC because it is not a generic Rev D XDC.

The pins marked in the document with red, are linked to the first 4 pins in the JA pmod connector. You can find them in the official XDC. 



You have two choices. Contact Avnet  and ask for that project specific XDC, or take the XDC from us and change it according to your project. 


Best regards,


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