Unspecified IO standard

[dmeads_10]

Hi all

trying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream.

[DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: io5_tri_o[0], LED4_tri_o[0], LED1_tri_o[0], switch_tri_i[0], and BTN1_tri_i[0].

I don't even have these ports in my axi gpio when I click on it.

here is my block diagram and constraints file:

##switch
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS33 } [get_ports { switch }];

##led4
set_property -dict { PACKAGE_PIN L15    IOSTANDARD LVCMOS33 } [get_ports { LED4 }];

##led1
set_property -dict { PACKAGE_PIN P14    IOSTANDARD LVCMOS33 } [get_ports { LED1 }];

##BTN1
set_property -dict { PACKAGE_PIN D20    IOSTANDARD LVCMOS33 } [get_ports { BTN1 }];

##io5
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { io5  }];

 

[artvvb]

Hi @dmeads_10

The error message is telling you that the port names you use in your XDC do not match the ones that are at the top level of the design (the HDL wrapper file).

The issue appears to be that the block diagram's ports are interface ports as opposed to just ports. Since interface ports could contain multiple buses (_tri_i, _tri_o, and _tri_t for example), they typically have an extra suffix tacked on when Vivado generates the HDL wrapper. There are a couple of solutions:

1. You could make the individual ports of the interfaces external, as opposed to the interfaces themselves. The names of non-interface ports are preserved in the wrapper file.

2. Open the HDL wrapper and review its port map to get the actual names of the ports as they are now, then use those names in the XDC.

Thanks,

Arthur