Digilent HS3 cable fails to detect the target Zynq Z7020 FPGA device

[varunnagpaal]

I recently purchased Digilent HS3 JTAG cable and wanted to configure PL of Zynq Z7020 device on a custom FPGA board called Snickerdoodle black

My overall setup is as follows:

• Software: Windows 7, Digilent Adept latest, Vivado 2018.2 with cable drivers installed
• Board files of my fpga board installed
• My Zynq FPGA board can boot Ubuntu 16.04 Linux flashed onto an SD card  and I can also connect to Wifi through it.
• Can connect to my FPGA board over USB-UART serially through teraterm

 

The board doesn't have the standard 14-pin Xilinx JTAG connector port and instead exposes majority of its multiplexed GPIO pins through up-facing connectors.  The JTAG interface to Zynq device is exposed as GPIO pins on the connector identified as J2 (see the 30-pin connector in top left corner of above board picture ).  I use jumper wires to manually wire the HS3 cable with the on board JTAG pins on the J2 connector. The relevant part of schematic as well map of JTAG wiring connections between HS3 and J2 connector are shown below:

 HS3 Pin                            Pin on J2 connector on board
1,3,5,7,9,11,13 (GND)     20 (GND, BLACK)
2 (VREF)                          25 (VCCO_0, RED)
4 (TMS)                           23 (TMS_0, GREEN)
6 (TCK)                            21 (TCK_0, YELLOW)
8 (TDO)                            24 (TDO_0, BLUE/PURPLE)
10(TDI)                            22 (TDI_0, WHITE)
12 —                                 —
14(SRST)                         19 (Zynq nRST/PS_SRST_B_501, ORANGE)

  

  

 

With SD card still inserted in the FPGA board and JTAG connections wired, I first plug-in the HS3 JTAG cable into USB port of my laptop. I then plug-in the micro-USB cable of FPGA board while holding the reset(SW2) button pressed, causing an on board white LED to start flashing. I wait for atleast 5 sec in order to skip booting Linux and instead go into JTAG mode. After releasing the button, the on-board white LED changes from blinking state to solid state indicating that the board is now in JTAG mode.

Next, I open Vivado. Create a new project with my custom FPGA board. I create a block design, add the Zynq IP , run block automation, add my custom IP, connect, run wiring automation, validate it, synthesize and implement it and write a bitstream without any errors. I then open hardware manager. I click auto-connect and it detects the Digilent HS3 cable. I also see the cable as USB serial converter under device manager. However, when I refresh target in hardware manager, it fails to detect the target Zynq FPGA device and shows me the following error:

 

Quote

open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server…
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2018.2
**** Build date : Jun 14 2018-20:42:52
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 904.773 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210299ABBF4A
ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210299ABBF4A.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
ERROR: [Common 17-39] ‘open_hw_target’ failed due to earlier errors.

 

I tried restarting my laptop to see anything changes but still it can’t seem to detect my target FPGA device. I have gone through my JTAG wiring again and it seems fine. If anyone spots any problem, please let me know. 

Would appreciate any help to get this running.

Thanks
V.

 

[JColvin]

Hi @varunnagpaal,

I asked one of our design engineers about this and they let me know the following:

"Based on the information that was provided the pin mapping appears to be correct. There’s a lot of extra wiring there which will add additional capacitance which may end up causing timing issues, depending on how fast TCK is running. I’d try eliminating half the length of wire… probably by plugging the flywire that’s coming out of J2 directly into the pins on the HS3. Another thing I would try is reducing TCK which can be done by connecting to a Local Target in Hardware Manager (don’t use Auto connect) and selecting a frequency as shown in the image here (attached below)."

Please let us know if you have any questions about this.

Thank you,
JColvin

 

[varunnagpaal]

@JColvin Hi. Thanks for the reply. I tried to directly connect flywires to the jtag cable thereby halving the wire length. Also changed jtag frequency to 10 MHz. I also tried all other frequencies. However the problem persists and my FPGA device is still not detected.

I get the same error as before:

Quote

ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210299ABBF4A.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.

[zygot]

Beware when purchasing FPGA boards that aren't designed to be configured through a standard JTAG connector, or have a COM port compatible with the FPGA vendors' configuration tools. The problem might be an open JTAG chain. It's not the HS3 cable. Time to get out the schematics and do a bit of studying up on how JTAG works.

[malexander]

@varunnagpaal

I took a brief glance at the Snickerdoodle schematics. There appears to be an arm processor (STM32F078VBH6) attached to the JTAG pins of the Zynq through RN9, which is drawn as 10 ohm series resistors. If the STM32 is driving the JTAG lines then the JTAG-HS3, or any other external programmer, will not be able to communicate with the Zynq due to a drive conflict. I didn't take the time to investigate this any further but if I were you my next step would be determining what the purpose of the onboard STM32 is and figuring out if it's supposed to somehow be used to communicate with the Zynq over JTAG. I suspect removing RN9 would solve the problem and allow you to communicate with the Zynq through the JTAG-HS3 but I think you should contact krtkl about JTAG functionality over header J2 prior to modifying your board.

Thanks,
Michael

[varunnagpaal]

Thanks for reply @malexander and @zygot. II will try and come back on this. Got busy somewhere else for now

[varunnagpaal]

On 11/13/2019 at 3:52 AM, varunnagpaal said:

Thanks for reply @malexander and @zygot. II will try and come back on this. Got busy somewhere else for now

@JColvin

Ok. So after long time I am back to working on this issue of HS3 not detecting my Zynq device on Snickerdoodle black SoC board. I tried your suggestions by plugging the flywire that’s coming out of J2 directly into the pins on the HS3 and reducing TCK but it still fails to detect my device.

"I suspect removing RN9 would solve the problem and allow you to communicate with the Zynq through the JTAG-HS3 but I think you should contact krtkl about JTAG functionality over header J2 prior to modifying your board."

@malexanderI also asked Krtkl about your suggestions and they say "Definitely don’t remove RN9’"

Any ideas how to debug this ?

 

[malexander]

@varunnagpaal

I still think your issue is the STM32F078VBH6. If Krtkl doesn't want you to remove RN9 then you should ask them the circumstances under which the STM32F078VBH6 drives the JTAG lines and how to get it into tri-state mode. If you have an oscilloscope you could try probing pins 2 and 7 simultaneously when the JTAG-HS3 is trying to drive TCK and if you don't see a clock signal of the same amplitude on both sides of the resistor then there is likely a drive conflict. If you post oscilloscope captures and tag me then I'd be willing to review them.

Thanks,
Michael

[varunnagpaal]

@malexanderjust wanted to update that I was able to detect my Zynq device using Xilinx Platform cable (DLC10). Now my HS3 cable seems to be detected by Vivado and Adept but still doesn't detect my Zynq device. 

[malexander]

@varunnagpaal

Unfortunately I don't have an answer for you. If I were debugging this I'd be probing the JTAG signals with an oscilloscope but I don't have the hardware here and I doubt I'm going to get authorization to purchase a Snickerdoodle for this purpose.