High Frequency Output from Nexys 4 DDR evaluation Board

[Luke Abela]

Good Day,

I am currently working on a project which entails the interfacing of a Nexys 4 DDR to a DAC8803EVM evaluation board. I am however having trouble connecting the generated clock of 50 MHz to the DAC. The DAC requires a clock of 50 MHz for optimal operation. Would it be too much to expect the IOBs of the nexys 4 ddr to output 50 MHz at the board connectors at full signal strength (i.e. minimal to no reflections), or has the board been predesigned with this situation in mind?

Kind Regards,

Luke

[zygot]

1 hour ago, Luke Abela said:

Would it be too much to expect the IOBs of the nexys 4 ddr to output 50 MHz at the board connectors at full signal strength (i.e. minimal to no reflections), or has the board been predesigned with this situation in mind?

You can find out timing information from the device data sheet provided from Xilinx. The slowest Artix devices will have no problem toggling IOs at 50 MHz as far as the IOB is concerned. Global clock signals in the slowest device is well above 50 MHz. As to the "at the board connectors" part there's the rub, so to speak.

Most Digilent low speed connectors have a 200 ohm current limiting protection resistor between the connector pin and the device pin. This limits the data rates for these PMODs. All of the Digilent reference manuals that I've looked at make this clear. They indicate that the regular PMODs are good for 10 MHz operation. Conceivably, if the FPGA pins are all outputs you could add termination at the DAC that you want to operate and do better than that.

I'm not sure what you mean by "full signal strength" but your constraints file can specify how much current a IO pin can source or sink. As to "minimal to no reflections" this can get complicated. Reflected energy is caused by impedance mismatches wherever they occur from the source to the terminus. This includes driver impedance, vias, branches etc. If a single-ended signal has a resistor stuck somewhere in the middle of a trace, has an unknown impedance with respect to ground, vias branches etc estimating how bad reflections will be  as well as a figuring out a  re-mediation strategy can be difficult though certainly not necessarily an insurmountable problem. I shouldn't have to tell you that driving more current into a badly impedance matched trace causes worse reflection problems as there is more energy bouncing back and forth. But this is one parameter that you can play with to minimize reflections.

Be aware that improper termination can cause all sorts of problems ranging from bad behavior to damage of the connected devices.

Read the Xilinx manuals. Read the board vendor reference manuals and schematics. Buy a board that is designed to let you do what you want to do. Don't buy a board and hope that you can overcome it's design choices to do what you want to do. In general Digilent boards are designed to be used with PMODs and whatever other interfaces are designed on it like Ethernet. The exception are the one's with and FMC connector. That doesn't mean that your Nexys Video can work with any high-speed device or FMC mezzanine card.