How to build your own RISC-V bitstream?

[aeon20]

Hello.

I'm trying to follow https://www.lowrisc.org/docs/debug-v0.3/fpga/ to build my own bitstream for the RISC-V.

There is a section just for that:
 

Quote

 

Generate the bitstream

FPGA demo with a trace debugger

cd $TOP/fpga/board/nexys4_ddr make cleanall CONFIG=Nexys4DebugConfig make jump

 

However, I can't find this folder. What am I supposed to git clone to get this directory structure?

I see that https://github.com/lowRISC/lowrisc-chip is referenced, so I've tried to clone that, and also lowrisc-nexys4, lowrisc-quickstart, and others. I can't find it.

Am I using an outdated tutorial? Maybe someone that got this working or simply has enough experience in general to see my mistake, could give me some pointers?

[D@n]

@aeon20,

You do realize you are on Digilent's forums and that Digilent has nothing to do with that design other than making the board it was demonstrated on?

Good.

It looks like the module you are looking for is part of https://github.com/lowRISC/lowrisc-nexys4 and that it has been incorporated into lowRISC/lowrisc-fpga and hence lowRISC/lowrisc-chip by using git submodules, and so those projects are referenced within the design of the lowrisc-chip but not actually contained within the project.  You'll need to do a git submodules init (don't trust me on the syntax) within the lowrisc-chip cloned repo to get these directories added into what you are looking for.

Dan