Question

Hello,

 

Im working on the following IP Integrator design. I have an Arty7 35T FPGA

I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are:

 - XADC: Input 0-3.33v  converted to 16bits. This one as a clock input ( CLK100MHZ )

 - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk )

My first idea was to connect Pmod DA3 clock to XADC clock creating a unique clock for the entire design. This design was validated. Creating a HDL Wrapper, it has a correct synthesis, implemetation and bitstream. Programing the board i dont get any analog value for output Pmod DA3, it only works output LED[15:0]. 

image.thumb.png.2ba9c033db3d865f58f511e5c4d1e3c7.png

Modules works correctly independently.

Should i make a different connection for clocks?

I dont know if there is a clock problem or other type problem.

i attach the project

Can anyone help me?

Thanks! 

XADC + DA3.rar

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Hi @Rodrigo_Montero

I don't think the issue is with the clock or with the XADC core, as you are seeing data on the LEDs, and the data on the LED line is synchronous to the clock.

The issue is likely due to the control signals for the SPI core and Pmod DA3.

First, If you look at the Pmod DA3 Reference Manual and AD5541A Datasheet, you can see that the MISO pin is replaced by an "LDAC" input to the chip. Data transferred over SPI is not actually output by the DA3 until this LDAC pin is brought low by the FPGA. Since your block design's MISO port is an input, you don't currently have any control over this. The default state of that pin might be low, so it might not be the cause of the issue, but controlling the pin is still important. Replacing the MISO port with an output of a const IP configured to output "0" should be sufficient.

Second, it is not clear how you are setting the external signals that control the SPI core. The ChipKit reset button looks like it will work as intended. I am less clear on the i_tx_start_0 signal. It looks like it should work fine as long as the Arty's JB2 pin is wired to VDD. (Though you may want to eventually expose the XADCdemo's ready_pe_strobe flag and data register to get more precise control over when SPI words are sent.)

Thanks,

Arthur

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