Nexys 4 DDR - UART ERROR

[AvaTRm]

Hi

I want to try UART communication from my Nexys 4 DDR board to my PC. But I have a wrong bits coming from my board. Why is that happen? I use the RealTerm program for read the serial port but it is showing "11000000" to me when all switchs off .

Thank you very much for your helps.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity UARTtx is
    Generic (
    CLK_FREKANS : integer := 100000000;
    BAUDRATE    : integer := 115200
    );
    Port (
    i_clk       : in std_logic;
    i_reset     : in std_logic;
    i_data_tx   :in std_logic_vector(7 downto 0);
    i_tx_start  : in std_logic;
    o_tx_out    :out std_logic;
    LED         :out std_logic_vector(7 downto 0)
     );
end UARTtx;

architecture Behavioral of UARTtx is


constant CLK_BIT    : integer := (CLK_FREKANS / BAUDRATE) + 1;
type t_UART_tx is (IDLE, START, SENT, DONE, OK);
signal r_UART_tx : t_UART_tx := IDLE;

signal r_clk_cnt : integer range 0 to CLK_BIT - 1 := 0;
signal r_data_indis : integer range 0 to 7 :=0;
signal r_data       : std_logic_vector(7 downto 0) := (others=>'0');
signal r_tx         : std_logic:= '1';
signal r_tx_tamam   : std_logic := '0';  
signal temp : std_logic;

begin
    o_tx_out <= r_tx;
    LED <= r_data;

    
    process(i_clk,i_reset) is
    begin
        if i_reset = '1' then
            r_UART_tx <= IDLE;
            r_clk_cnt <= 0;
            r_data_indis<= 0;
            r_data      <= (others => '0');
            r_tx        <= '1';
            r_tx_tamam  <= '0';
        
        elsif rising_edge(i_Clk) then
        temp <= i_tx_start;
        r_tx_tamam <= '0';
            case r_UART_tx is
                when IDLE =>
                    r_tx <= '1';
                    r_data_indis<= 0;
                    if temp='0' and i_tx_start='1' then
                        r_data <= i_data_tx;
                        r_UART_tx <= START;
                    end if;
                       
                when START =>
                    if r_clk_cnt = CLK_BIT - 1 then
                        r_tx <= '0';
                        r_UART_tx <= SENT;
                    else
                        r_clk_cnt <= r_clk_cnt + 1;
                    end if;
                
                when SENT =>
                    r_tx <= r_data(r_data_indis);
                    if r_clk_cnt = CLK_BIT - 1 then
                        r_clk_cnt <= 0;
                        if r_data_indis = 7 then
                            r_data_indis<= 0;
                            r_UART_tx <= DONE;
                        else
                            r_data_indis <= r_data_indis +1;
                        end if;
                    else
                        r_clk_cnt <= r_clk_cnt + 1;

                    end if;
                    
                when DONE =>
                    r_tx <= '1';
                    if r_clk_cnt = CLK_BIT - 1 then
                        r_clk_cnt <= 0;
                        r_UART_tx <= OK;
                    else
                        r_clk_cnt <= r_clk_cnt + 1;
                    end if;
                    
                    
                when OK =>
                    r_tx <= '1';
                    r_tx_tamam <= '1';
                    r_UART_tx <= IDLE;
                   
                when others => NULL;
            end case;
        end if;
    end process;
end Behavioral;

 

[artvvb]

Hi @AvaTRm

Simulating your design is a very good approach to debugging stuff.

I ran your file against a simple testbench (written in Verilog and pasted below) in Vivado's simulator. It looks like, (1.) you are not sending a start bit, and (2.), the r_data_indis counter is rolling over before you send the last few bits of your byte (this is why those "1"s are showing up). See the timing diagram below.

// uart_sim.v

`timescale 1ns / 1ps

module uart_sim;
    reg clk = 0;
    initial begin
        #5;
        forever #5 clk = ~clk;
    end
    reg reset = 1;
    initial begin
        #20 reset <= 0;
    end
    reg [7:0] data_tx = 8'h00;
    reg tx_start = 0;
    initial begin
        #40 tx_start <= 1;
        #50 tx_start <= 0;
    end
    wire tx_out;
    wire [7:0] led;
    UARTtx #(
        .CLK_FREKANS(100000000),
        .BAUDRATE(115200)
    ) dut (
        .i_clk(clk),
        .i_reset(reset),
        .i_data_tx(data_tx),
        .i_tx_start(tx_start),
        .o_tx_out(tx_out),
        .LED(led)
    );
endmodule

 

Hope this helps,

Arthur