Is it possible to use the Cmod A7 and/or Cmod S6 as a SPI master (mosi and miso)?

[Takemasa Tamanuki 0]

I am driving DACs (up to 50MHz clock, 24bit command) using a SPI-bus by AD2 right now and I am trying to drive the DACs by FPGA.

This might be basic, but could you tell me the following queries about the products of Cmod A7 and/or Cmod S6.

Q1: Is it possible to use the Cmod A7 and/or Cmod S6 as a SPI master (mosi and miso)?

If yes,

Q2: How many SPI-slaves can we control by the Cmod A7 and/or Cmod S6? (Is it possible to control 8-slaves?)

Q3: What is the clock-speed of the Cmod A7 and/or Cmod S6? (Is it fixed clock-frequency? Or variable?  10MHz, 20MHz or 50MHz are possible?)

Q4: What is the program language is used for the FPGA program of the the Cmod A7 and/or Cmod S6? (Can I use Python?  Or HDL only?)

Q5: Can we introduce a “pause (for example 0.01msec, 0.1ms, etc. ) routine” into the FPGA program of the the Cmod A7 and/or Cmod S6?

[xc6lx45 137]

Hi, quick answer: For someone with FPGA design experience it is not a big job (the PC side interface for configuring parameters etc is probably more work than the SPI core itself). BUT, don't underestimate the difficulty of getting there ("Python?", I read between the lines that you need it as just a tool, not a task that may require a man month. Check early what is realistic - whether or not the hardware can do the job is not necessarily the right question. A FPGA can do "anything", more or less using HDL)

It has built-in PLLs so you can generate any frequency you like. 100 MHz is fairly straightforward, 200 MHz will need some extra effort, 400 MHz should be feasible in the hands of someone who knows the hardware (SERDES) . As many slaves as you have IO pins for (check the voltage, though).

SPI is fairly simple, it sounds like a fairly compact project (UART for PC IO, state machines for control around a bunch of shift registers). But again, reading between the lines, be careful what is achievable with the amount of time you are willing to invest.

 

[xc6lx45 137]

PS not saying that the idea of 400 MHz SPI is necessarily meaningful 🙂 just talking about the internals to the FPGA pin, not what's realistic on a PCB with 1/10 inch headers etc.

[zygot 154]

7 hours ago, Takemasa Tamanuki said:

Q1: Is it possible to use the Cmod A7 and/or Cmod S6 as a SPI master (mosi and miso)?

Almost certainly, depending on clock rate.

7 hours ago, Takemasa Tamanuki said:

Q2: How many SPI-slaves can we control by the Cmod A7 and/or Cmod S6? (Is it possible to control 8-slaves?)

Sure, generally the master provides chip select control signals to each SPI slave as sort of a crude addressing scheme. If your slave doesn't have a CSn pin then you might need to be creative. When you tap off a signal many times for multiple devices you are likely to create signalling issues that can render even a good SPI master design unusable. This is digital design using real components and subject to physics.

7 hours ago, Takemasa Tamanuki said:

Q3: What is the clock-speed of the Cmod A7 and/or Cmod S6? (Is it fixed clock-frequency? Or variable?  10MHz, 20MHz or 50MHz are possible?)

The CMOD A7 devices have clock management hardware so you can take any input clock and create a lot of different output clocks for your design. If you look in the project vault you will see that my projects use a 100 MHz global clock. This answer isn't quite sufficient if I am getting the drift of your real question. I've done a lot of FPGA SPI designs and all of them use a logic derived SCLK instead of a global clock. For high data rate applications this is usually a  bad practice. For low speed designs, as long as the FPGA tools doesn't know that SCLK is really a clock the designer has greater flexibility in meeting timing requirements by using SCLK derived from logic. It all has to do with delay management.

7 hours ago, Takemasa Tamanuki said:

Q4: What is the program language is used for the FPGA program of the the Cmod A7 and/or Cmod S6? (Can I use Python?  Or HDL only?)

There are people and companies promoting Python to verilog or VHDL code. Some work out better than others. All of them, despite a few nifty examples, are no substitute for learning a good HDL like Verilog or VHDL. Your question suggests to me that ytou need ot start with understanding what an FPGA is, and proceed from there. I am not a believer in any promises to make very complex subject trivial by removing the complexity.

 

7 hours ago, Takemasa Tamanuki said:

Q5: Can we introduce a “pause (for example 0.01msec, 0.1ms, etc. ) routine” into the FPGA program of the the Cmod A7 and/or Cmod S6?

Now I know that you need to start by learning what an FPGA is. It sure ain't a microprocessor.

Now that I've provided answers to your questions I need to make a clarification. I've replied as a long time HDL FPGA designer intending to design my own SPI master. You can also use canned IP using the Xilinx preferred board design flow. To me this is in the realm of doing FPGA development using Python. It is possible to create a result that appears to solve a problem without actually understanding any of the details involved in getting there. That's the promise that FPGA vendors hope that their IP GUI board design flow will make customers out of those not wanting to spend the time learning the details. I'm not a believer in that concept either.

Edited September 25 by zygot

[Takemasa Tamanuki 0]

Dear xc6lx45_san and zygot_san,

Thank you very much for your detail comments about the FPGA-module product of Cmod A7 and Cmod S6.

Actually, the AD2 is introduced into my existing SPI-circuit-system (8-slaves-SPI (MOSI): 16pcs-DACs are included in the each slave. That is 128pcs-DACs for 8-slaves.) and I am considering to introduce a FPGA into the programmable-control of SPI.

Because, I am thinking that we can speed up the program-executing-time by introduction of FPGA instead of AD2 due to eliminate the USB-communication-time on the AD2-case.

 

>> It has built-in PLLs so you can generate any frequency you like.

> The CMOD A7 devices have clock management hardware so you can take any input clock and create a lot of different output clocks for your design.

In my existing AD2-SPI-circuit-system, I am driving it with clock-speed of 10MHz.

For my double checking,  the CMOD A7 can create 10MHz SPI_clock (by PLL). On the other hand, the Cmod S6 can not create 10MHz-clock since it has no PLL.  Am I right?

[zygot 154]

The Spartan7 devices, like those on the CMOD-A7 have clock management tiles like the other Series 7 devices. The Spartan7 devices are a low cost spin of the Artix, which used to be the low cost Series7 device family. They just have reduced performance and fewer resources to go along with that lower cost. You need to read the family datasheet and overview reference material to understand what it is that you get for your money. Lower cost devices don't necessarily translate into substantially lower cost boards.

As to clock management resources creating any clock frequency from any input clock, there are caveats. Unless you know what you are doing I reccomend that designers use the tool clock wizard IP when using PLLs or MMCMs. The quality of the output clock is not the same for any frequency and the default settings of the wizard limit available output clock rates depending on a preset level of jitter. Yes, you can instantiate a PLL or MMCM as a macro and choose any ouput frequency but that doesn't mean that you will get that exact frequency or that it will have the quality that you want. That's the nature of all PLL architectures.

In general, one reason for using an FPGA is that you have greater control over timing and executing concurrent processes relative to a micro-controller.

Using a PLL to create an SPI SCLK introduces its own set of problems but is certainly an option. You need to understand the timing specification requirement of the slave devices in order to make a good decision for the master SPI design.

Edited September 26 by zygot

[Takemasa Tamanuki 0]

Dear zygot_san,

Many thanks for your detail comments.

I purchase ordered the Cmod-A7(35T) today and it will be shipped to us tomorrow.

BTW, do you have reference FPGA-configuration program of SPI-driving-circuit? I would like to configurate the FPGA as “driving circuit of 8-slaves SPI (MOSI only)”.

Also, do you have reference run-program (SRAM table) of the SPI-driver-configurated-FPGA?

I would appreciate if you could provide them to me.

Thanks.

[zygot 154]

@Takemasa Tamanuki

If you intend to use the the CMDO A7 as a standalone component you need to carefully read the reference manual and schematic. This module is meant to be powered by the same USB connector that provides JTAG configuration and UART communications. It has a FLASH device capable of configuring the FPGA and a power input pin so it is entirely possible to use the module without USB connectivity.

When I develop an interface using a standard like SPI I don't write HDL that supports all of the possible modes that might exist in every device. I design a minimal interface that supports a particular device. I'm sure that there is good IP for SPI masters out there but I've never used one so I have no suggestions. If you can do Verilog or VHDL development and understand how the SPI devices that you are working with operate it is a rather easy and straight forward effort.

I advise against expecting that adding an FPGA board with generic "code" could be an easy and quick solution to any existing problem.

[D@n 412]

@Takemasa Tamanuki,

I'm going to have to second much of what @zygot just said.

13 minutes ago, zygot said:

When I develop an interface using a standard like SPI I don't write HDL that supports all of the possible modes that might exist in every device. I design a minimal interface that supports a particular device. I'm sure that there is good IP for SPI masters out there but I've never used one so I have no suggestions. If you can do Verilog or VHDL development and understand how the SPI devices that you are working with operate it is a rather easy and straight forward effort.

I advise against expecting that adding an FPGA board with generic "code" could be an easy and quick solution to any existing problem.

But let me go a bit further, and give you some rope to hang yourself with: here's a discussion of an SPI design used to control a flash chip.  Yes, it comes with source code.  My guess is that you'll decide this doesn't do the job--especially since I've built multiple SPI controllers and none of the others look like this one.  As @zygot suggested, this is really a "tailed-to-device" operation.  Still, perhaps it might help you consider all of what it takes to design an interface, and so I offer the link above.

Dan

 

 

[Takemasa Tamanuki 0]

Many thanks for your comments.

I started to learn and handling of the CMOD-A7(35T) and the “blinky.v” is successfully worked on my CMOD-A7 (on Vivado 2016.4) based on the “Getting Started with Vivado”.

Next, I am trying to store the project by referring the “How To Store Your SDK Project in SPI Flash”.

https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start

 

Q1: I did the “0. Compress Bitstreams (Optional)” (<-- check the “-bin_file*[V]” and set “Enable Bitstreem compression [TRUE]”),

> 0.6) Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project.

> Select [Generate Bitstreem] and a window might pop up asking you to save your XDC. If so, give the XDC a name and save it. Your bitstream should start generating afterwards.

However the “window might pop up asking you to save your XDC” is not shown in my window.

Please let me know, How to show this pop-up?

 

Q2: On the following section of the “1. Create a SPI Bootloader Application”,

> 1.2) Select SREC SPI Bootloader and select Finish.

However, the “SREC SPI Bootloader” is not shown on the “Available Templates:”.

Please let me know, How to show this pop-up?

 

Thanks,

T. Tamanuki

[Takemasa Tamanuki 0]

The Q2 statement is revised.

[Wrong] Please let me know, How to show this pop-up?

[Correct] Please let me know, How to show this “SREC SPI Bootloader” Templates?

Actually, I am using a “Xilinx SDK 2019.1”.

[Takemasa Tamanuki 0]

My requesting about to know the “storing the configuration program to Flash-memory” is solved by learning the

“2. Creating Program File” of “Cmod A7 Programming Guide”.

So, no need your answers for the Q1 and Q2.

I'm sorry to interrupt you.