LVDS in CMOD S7

[Alberto Vigato]

I'm using a CMOD S7 board and I intend to use a couple of LVDS output pairs.
I set the output pairs in Vivado as LVDS_25* and it is regularly synthesized.
But I don't see any output on those pairs, and it is probably due to the power supply to the FPGA bank involved.
My question is: can I use this kind of LVDS output on this evaluation board?

[zygot]

1 hour ago, Alberto Vigato said:

can I use this kind of LVDS output on this evaluation board?

All of your questions can be answered by reading two documents. Read the 7Series_SelectIO user's manual. Read the schematic for your board. [edit] Ok, for low end parts like the Spartan7 you may need to read the datasheet so make sure that you device supports a particular logic standard.

One answer is that you can do pretty much anything if you are designing an FPGA board. If you are buying an FPGA board then your options are somewhat limited. If you have low performance requirements you still might be able to do what you want to do, but here is the best advice you will get:

Don't buy a board and then try and make it do something that it wasn't designed to do. Instead, choose your project and define its hardware requirements. Then research available boards suitable to your budget by reading documentation and the schematics. If you can't find enough information indicating the a particular board will absolutely work for your project, keep looking. It all starts with PCB stackup design, IO Bank Vcco selections, GPIO pin assignments, connector choices, and signal routing. All of the choices made there determine the maximum usability of a board for any particular purpose.

For high performance designs it's easy enough to design a board badly using high quality SMT parts. Trying to overcome board design decisions limiting performance with add-on hardware is usually not going to provide the results you want.

For expensive board I suggest that you create a rough approximate of your project design and implement it in Vivado or whatever tools are appropriate. That doesn't mean that you are guaranteed success, just that you are less likely to waste money on hardware sitting around waiting for a suitable project.

The first task to achieving success for any project is.... preparation. If there is a good rule to follow it would be this: Since you have to do the logic design anyway why not do it first, at no expense, using the development tools to achieve a bitstream that makes timing and works in simulation,  and getting a feel for what surprises lie in wait before committing to hardware that adds more complexity?

[Alberto Vigato]

Thank you for your prompt reply zygot but unfortunately you're not answering to my question.

[xc6lx45]

disclaimer, I haven't tried a similar thing and did not dig into the documentation. But I think you need a HP bank (not HR) and question is, does a low-end board support it. Check the warnings.

See https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 91:

The LVDS I/O standard is only available in the HP I/O banks.

There used to be LVDS 3.3 but not on 7 Series anymore, AFAIK (differential modes, yes, but not "LVDS" specifically).

[zygot]

4 hours ago, Alberto Vigato said:

you're not answering to my question.

Well I guess that we disagree on that. I've posted direct answers to this basic topic so many times on this forum that I figure that perhaps being direct isn't the correct approach. You can answer all of your own questions by following the advice that I've provided. Everything that I mentioned in my reply is pertinent to your inquiries.

I've looked at the schematic for your board. Have you? Did you bother to read the warnings from the tools? I'm surprised that bitgen didn't exit with errors.

I will add one more piece of advice.

If all you want to do is play ( I don't mean to use play with any pejorative connotations ) in the PMOD-centric sandbox that most of Digilent's board are designed to be used then stick to what they provide in terms of support. The CMOD boards are actually a bit more dangerous because they seem, to the novice, to invite playing outside the sandbox. If you are going to do your own hardware interfaces then you had better be able to read and understand the vendor's literature. If you don't understand it then you should have an idea of what you need to do in terms of self=education; and realize that you also don't have the tools to evaluate any answers you might get from a third party who really dosn't have enough information to provide the answer that you want.

[zygot]

4 hours ago, xc6lx45 said:

disclaimer, I haven't tried a similar thing and did not dig into the documentation. But I think you need a HP bank (not HR) and question is, does a low-end board support it. Check the warnings.

This post serves as the ideal example for my warnings for those with questions and those with answers to proceed sith caution.

Xilinx documentation, similar to the scriptures, does not work so well for people looking for  a line of text that seems to answer a particular question or prove a point. Both religious and technical texts require, for different reasons perhaps, that the seeker of truth be willing to commit to reading the whole book in order to gain knowledge. @xc6lx45got to (one of) the correct pages of the Series 7 user's manual but stopped short taking time to read all of the pertinent text. The line quoted says: 

The LVDS I/O standard is only available in the HP I/O banks. It requires a VCCO to be
powered at 1.8V for outputs and for inputs when the optional internal differential
termination is implemented (DIFF_TERM = TRUE).

But just below that line is this:

The LVDS_25 I/O standard is only available in the HR I/O banks. It requires a VCCO to be
powered at 2.5V for outputs and for inputs when the optional internal differential
termination is implemented (DIFF_TERM = TRUE).

Sometimes the holy texts are stumbling blocks to those who aren't committed [to careful reading and pondering the implications of the lines in context of the whole text].

A lot of bad decisions and evil behavior are the result of bad hermeneutics.

Fortunately, xc6lx45 is not only a very smart guy but circumspect. It just so happens that his answer led off with a warning followed by incomplete and in this context wrong advice.  The forum format invites knowledgeable people short on time to provide confusing and erroneous advice despite their desire to be helpful. Buyer beware.

To add a bit of insight to the complexity of a seemingly simple question when one throws around the term LVDS in the context of hardware interface design it matters what the interface connects to on both ends. Differential signalling is a topic of which only a small part has to do with FPGA devices.

In the context of this discussion one needs to keep on reading. The section dealing with termination might be helpful.

One final thought. The LVDS_25 IOSTANDARD works out better on HP IO Banks than HR Banks for Series7 devices; assuming that the board designer doesn't screw it up. The answer is in the holy text.

 

[cchamp]

Hi,

 

I have the same problem with a CMOD A7 board.

Does all this mean that these boards have been designed without any chance of using LVDS  outputs ?!

Regards

[zygot]

3 hours ago, cchamp said:

Does all this mean that these boards have been designed without any chance of using LVDS  outputs ?!

In all practicality, all of the boards like the CMOD using Series7 devices that only provide 3.3V for the IO Bank Vcco are incompatible with LVDS. Digilent isn't the only company making this faux pas; the Red Pataya got this wrong as well. I'm sure that they aren't alone. Furthermore, even vendors like Opal Kelly who offer user select-able Vcco for some IO banks or user supplied Vcco don't match multiple LVDS pairs to a level suitable for easy multi-lane LVDS interfaces. Finally, most data LVDS applications are source-synchronous so you need at least one clock capable LVDS pair for a clock input or output.

Buyers who want to do specific things with FPGA boards are responsible for doing their own homework prior to sending a vendor money for a particular board. Understand that there are limited things that you can do in a cheap, limited layer, tiny module with regard to signal routing and power supply options.

Practicality aside, you can, in theory, connect just about anything to your GPIO with the proper external conditioning components providing a suitable level of compatibility for a given IOSTANDARD; it just isn't likely to be cost effective or high performance.  

I should note that discussions of LVDS as an FPGA IOSTANDARD is separate from discussion of LVDS in general.  Using FPGA pin pairs as "LVDS" inputs is a bit different than using FPGA pin pairs as "LVDS" outputs. There are a lot of LVDS interface components out there. You have to be able to understand and analyze the IO specifications to determine compatibility. For Xilinx Series7 device consult the data sheet for your device as well as the Series7 Select IO Reference Manual. For Intel device consult the device Handbooks. For specific LVDS interface  chips consult the vendor datasheets and applicaiton notes.

Opal Kelly did get LVDS right in it's SYZYGY standard and products. Digilent will provide an FPGA board with SYZYGY ports **soon**. Unfortunately, the ARM architecture of the Eclypse board is a bit of a bottleneck for high data rate applications; but many will find the ecosystem very useful though perhaps a bit more complicated than necessary. That's the cost of 'Plug 'n Play'. I would expect IC vendors to latch on to SYZYGY as the standard for their EMVs as adoption gathers steam. I can think of a lot of components out there that are simply too much for the tired old 12-pin PMOD but would work quite nicely with SYZYGY. The connectors are capable of high speed interfaces but not beyond what a low budget developer can design PCBs for.