MTDS PMOD Connection issue

[WillTx]

Trying to connect the MTDS PMOD to my CoraZ7-07S FPGA board. I used the Digilent MTDS IP but I'm having trouble figuring out how to connect it to PMOD port JB on the Cora board. Read on another answer that I should use JD by default but that's not an option in Cora. Vivado (2019.1) also warns that the IP was packaged for arty board but assume that's not an issue for me other than the JD issue.

I saw on another post that I need to edit the XDC file to change the PMOD connector but I don't see how I can do that since the MTDS PMOD doesn't show on my constrains file. Thinking about wiring it manually. Any suggestions? Would appreciate any help.  

[WillTx]

Solved, issue with manually generating the design wrapper file. Had to let it do it automatically to figure out what it wanted.

[Ana-Maria Balas]

Hello @WillTx,

1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :

https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 

You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.

2. Your block design after adding the Pmod MTDS IP:

3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.

If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/

 

Cheers,

Ana-Maria

[WillTx]

Hi Ana Maria, thank you for such a detail answer, really appreciate it. I'm familiar with all the documents you  mentioned above but still having issues getting the display  to work. I'm prototyping a design that already have a couple of different PMODs and everything was working fine but adding the display has been a challenge. I ended up adding the pinout manually to the XDC file not the way you show above but like this:

set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MTDS_Pmod_out_0_pin1_o }]; #IO_L8P_T1_34 Sch=jb_p[1]

I had to figure out which pins were inputs or outputs because I didn't know I could use the _io subfix to attach everything to the pin interface. I will change it to the way you suggested any way.

I'm not able to click on the PMOD port on the board as indicated on the PMOD user guide. The user guide is very outdated, I'm on Vivado 19.1 and it looks nothing like what's on the document. I have tried creating my project from scratch multiple times specifying the Cora board as the platform but the Board tab only shows initially. Once I close Vivado and come back the Board tab is gone and it is grayed out on the Windows menu. It does export the board information to the SDK fine.

The issue I'm having now I think is due to the following critical warning:

[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports ext_spi_clk]'. ["c:/Box/Engineering/Electrical/Xilinx/Projects/HW/Cora-Z7-07S-TOP/Cora-Z7-07S-XADC.srcs/sources_1/bd/design_1/ip/design_1_PmodMTDS_0_0/src/PmodMTDS_ooc.xdc":9]

This constrain is supposed to only be relevant for out of context synthesis but it keeps coming up when I do top level synthesis and implementation and I think this might be why the MTDS header files are not being exported to the SDK. I'm thinking about going to the packaged XDC file and commenting out this line. Any suggestions? Vivado 19.1 doesn't seem to like it.

 

[Ana-Maria Balas]

Hello @WillTx,

Can you put here a screenshot of your block design ?

The block design I posted above is from the project I created using  Vivado 2019.1 and the Pmod MTDS IP from vivado-library. Then I imported the Example Project in SDK and it's working fine.

If you want to use the board flow, as suggested in the tutorial, you need to install the board files first. Then add the Cora Z7 board when creating the project :

Then you need to follow the tutorial. Even if the tutorial was made with a different version of Vivado, the steps are the same.

Why do you need  "ext_spi_clk" ?

If you don't have an external pin named "ext_spi_clk" in your design but you constrained it in the xdc file at PL System Clock, you get that error.

 

 

 

[WillTx]

Hi Ana-Maria,

I do have all the board files installed. And I did manage to get Vivado to hold the Board value so now I can see the board tab. But adding the PMOD through the board as in the tutorial introduces a different set of issues.

I have created a new project with only the MTDS PMOD to simplify the design. In the first image you can see the critical warnings, the first set is related to DDR negative slack, known issue with the Cora board. The last one is the one I referred to  related to ext_spi_clk. This has nothing to do with me, it is because of some constraint in the PMOD OOC XDC file. I'm ignoring that one too for now. But you should be seeing the same unless you are using an unpublished version of the MTDS IP.

 

The problem I have now with the demo project is that I don't know what I need to do to connect the _i, _o and _t ports on the PMOD to the physical pins. It is not happening automatically. Note also that when I add the PMOD by right-clicking on the JB port of the board (as suggested by tutorial), the external port is created automatically but is called "jb", not like in your block diagram. Again, I'm wondering if you have an unpublished version of the PMOD that works better. You can see below the error messages that Bitgen produces and if you look at the implemented results, there are different pins assigned to each of the _i, _o and _t signals.

I didn't include the block diagram of the demo project but it looks just like yours, only that the external port name is "jb" instead of "MTDS_Pmod_out_0"

[WillTx]

Please, confirm that I don't need to worry about the following critical warning message:

I tried removing the "jb" port interface that was automatically added when adding the MTDS IP and then generating a new interface type Digilent PMOD. That resulted in a port interface that is named just like in your block diagram but still doesn't work. Synthesis and implementation complete fine but Bitgen still fails the same way:

 

At this point, I have no clues of what the issue is and I'm out of ideas.

[Ana-Maria Balas]

In my block design I didn't used the board flow, I made external the output pin of the IP , and then I used that name to constrain the JB Pmod pins in the Cora-Z7-07S-Master.xdc constraint file(as you can see in the picture below the bd) .

You have two choices:

1. You can name the Pmod's IP output anyway you want, but then you'll have to constrain the Pmod pins in the xdc file as I did in my block design 

2. You can use the board flow as suggested in the tutorial, and you don't use the xdc file. "jb" is the name of the Pmod connector, as it is supposed to be, you cannot change it. 

When you connect it from the board tab, it means that the output of the Pmod IP will be constrained automatically to the right pin connector( named "jb") of your board, and this way you don't have to constrain those pins manually.  

 Those warnings won't affect your project, it means that the Pmod MTDS IP was packed with a different board when it was created.

Just add the Zynq, add the Pmod MTDS using board flow, leave the "jb" as it is, ignore the warnings related to different board value of the Pmod MTDS IP, make sure you validated your design, create HDL Wrapper and generate bitstream.

Then follow the rest of the steps from the tutorial. 

 

Cheers,

Ana-Maria

 

[Vitalii S.]

There are few tricks to make it work on Vivado 2019.1 and zybo z7-10.

1. Don't use archived IPs by Digilent. Download master branch instead. (for me it was the reason of few easy-solvable problems)

2. Don't forget to follow each step, described in README.md of PMOD_MTDS and uncomment the DemoTest number in the source code.

3. Keep in mind that demos that need SDcard with images will not start without the card with content.

vivado 2019.1 project