Does the GPIOs in Digilent boards length matched?

[ManserDimor]

Hello

I would like to know if the GPIOs in Digilent boards are length matched.

Thanks

[zygot]

8 hours ago, ManserDimor said:

I'm not interested in any particular connector, anyone offering length matched pairs will do it.

Re-read my previous post. Your initial question is why bad assumptions will get you bad advice. You assume that length matching traces implies something that it doesn't.

8 hours ago, ManserDimor said:

Actually I'm asking this question because I need to interface with high speed ADC via LVDS.

Read  ahead...

8 hours ago, D@n said:

You'll need something that is voltage agile if you want to do LVDS

@D@nhas offered a good hint to your question.

 

On 9/29/2019 at 2:09 PM, zygot said:

The only 3.3V differential IOSTANDARD supported by Series7 devices is TMDS and this is best done when the termination is as close to the receiver as possible.

This quote is from my earlier post to this thread.

I hate repeating myself but I realize that finding answers already covered by such questions isn't easy on this forum.

1. High speed LVDS used in ADC device interfaces are only supported by IO Banks with Vcco of 2.5V or lower.
2. Digilent has a number of FPGA boards with FMC connectors whose signals are connected to Vadj. Vadj is user selectable on most FPGA boards with FMC connectors that I'm aware of.
3. Even if you choose a board with an FMC connector with IO Banks powered by Vadj = 1.8V, 2.5V or some other voltage compatible with Series7 LVDS IOSTADNARDs that doesn't mean that any ADC mezzanine board with and ADC will work with it. There are restrictions for clocking options using Series7 SERDES options.
4. I have investigated using the Nexys Video, Genesys2 and KC705 boards with various ADC EVMs involving multi-lane LVDS interfaces. I haven't found any EVMs that work with any of those FPGA boards due to clock pin assignments.
5. Connector choice is very important.
6. Opal Kelly has a few boards with their SYZYGY specification ports that are properly designed for mixed LVDS and single-ended interfaces.

If you want to interface an LVDS device to your FPGA you need to read and understand the Series7 Select IO and Clocking reference manuals as a starting point. You need to examine the schematics for any potential FPGA board platform. Opal Kelly offers one 25 MHz dual ADC POD. I'm unaware of inexpensive ADC add-on boards for Xilinx otherwise. You can always design your own ADC FMC mezzanine card but be careful in assigning signals. If all your clocks and data are on the same IO Bank then you have a chance. LVDS interfaces where the data runs at a rate > 8x the clock rate have additional restrictions to observe and likely you need 2 clocks.

I'm not happy to say this but if you want to do ADC or DAC conversion at rates of 100 MHZ or higher things the Intel HSMC world is where to look. If money is no object than there are military grade options in the Xilinx world but I doubt that you get much support. The most important advice is to be aware of the rules for high speed LVDS in your FPGA device and synthesize and route a preliminary design with pin assignments before making  a purchase. If you know what your are doing it isn't hard to design an interface or layout a board that won't work. If you don't know what you are doing you don't have much chance of success.

There are multi-channel ADCs in the 250 MHz range with parallel DDR interfaces which are a whole lot easier to work with.

Much of what I've mentioned here were  previously mentioned in a few threads in the Technical Based Off-Topic Discussion forum. You can search the Digilent Forums for posts relating to particular topics.

Lastly, you just aren't going to find a cheap FPGA board that let's you implement a state of the art high speed interfaces.

 

 

[vicentiu]

Support confirmed that the platform does not currently support changing the default sorting, but I've added a feature request to them.

[vicentiu]

You have sort buttons right below the main post, but it always defaults to Votes when you open a thread.

I'm waiting on a reply from support it can be defaulted to Date.

[vicentiu]

1 hour ago, zygot said:

Today, when I try to read through this thread again I find the posts to be out of chronologic order. This makes the conversation very hard to follow and adds considerable confusion to anyone trying to grasp a conclusion to the important issues raised. I find this very bizarre and disturbing. 

The wisdom of promoting the viewing order of replies to questions based on an opinion as to whether or not a particular answer resolves the question is, as a service to the forums readers, debatable. If doing so muddies the waters, so to speak, or is designed shape the discussion without adding content then I think that it should be avoided.

Thanks for pointing that out. That does make it pretty confusing.

I'll contact the forum developers to see if there are options we can tweak to turn that off.

[zygot]

Today, when I try to read through this thread again I find the posts to be out of chronologic order. This makes the conversation very hard to follow and adds considerable confusion to anyone trying to grasp a conclusion to the important issues raised. I find this very bizarre and disturbing. 

The wisdom of promoting the viewing order of replies to questions based on an opinion as to whether or not a particular answer resolves the question is, as a service to the forums readers, debatable. If doing so muddies the waters, so to speak, or is designed shape the discussion without adding content then I think that it should be avoided.

[ManserDimor]

@zygot @D@n  Thank you very much for your clarifications. I've got lot of information that I wasn't even aware of and that I've never found anywhere.

I see that interfacing high speed ADCs (> 100MSPS) isn't as easy as I imagined it when using LVDS. I believe that I have to forget about it and go for parallel DDR as I can't afford those expensive boards.

[zygot]

I own three of FMC equipped boards that  you mention and frequently use at least one on a regular basis. Just for arguments sake; lets say that I want to design my own FMC mezzanine card using all of those differential pairs. Where do I find the trace routing report letting me know what the trace lengths are for the Genesys2, Nexys Video and Zedboard?

 

[zygot]

3 hours ago, vicentiu said:

FMC is your best bet since the standard imposes length matching.

Not sure about best bet being a good enough reason to spend money. I'm not sure what the statement even means. I do know how do design high-speed differential signals on PCBs.  Do you have a specific point to what precedes your last post that you see as incorrect or misleading?  The quoted statement implies that you do. Can you also name all of ( or just one ) the FMC mezzanine cards having a high-speed single or multi-channel ADC with LVDS interface that Digilent has verified and warrants to work with all ( or any ) of those FPGA development boards? That would more helpful to your potential customers.

[vicentiu]

FMC is your best bet since the standard imposes length matching.

Here are our boards with FMC:

https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/

https://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/

https://store.digilentinc.com/genesys-2-kintex-7-fpga-development-board/

https://store.digilentinc.com/netfpga-1g-cml-kintex-7-fpga-development-board/

https://store.digilentinc.com/netfpga-sume-virtex-7-fpga-development-board/

[D@n]

@ManserDimor,

You'll need something that is voltage agile if you want to do LVDS.  Most of the I/O on Digilent boards is fixed at 3.3V, so check your reference manual and your schematic to make sure that you can use the voltages available to you.

Dan

[ManserDimor]

5 hours ago, vicentiu said:

Which connector are you interested in?

I'm not interested in any particular connector, anyone offering length matched pairs will do it.

[ManserDimor]

On 9/29/2019 at 7:09 PM, zygot said:

Final comment. If you are going to connect an external board or device to your FPGA board connector then you must assume the digital logic designer role required to do so.

Actually I'm asking this question because I need to interface with high speed ADC via LVDS.

If I'm not wrong, length matched pairs are mandatory.

[vicentiu]

On 9/29/2019 at 1:54 PM, ManserDimor said:

Hi vincentiu

I appreciate your help.

What about the Arty A7, Arty Z7 and Zybo Z7?

Thanks

Which connector are you interested in?

[zygot]

@ManserDimor

Here's a general rule of thumb. Differential traces, whether laid out as differential or not must be length matched as best as possible. High speed bussed signals are usually length matched but normally this isn't nearly as critical as differential signalling; and this is usually done with a maximum data rate in mind. Everything else is usually assigned to the auto-router. Hand tuning traces is expensive and time consuming and usually there are a limited number that can be optimised with high ball count FPGA footprints. Usually, the focus is on external memory like DDR.

If you need IO pins that are length matched then choose a board that makes it clear how well this was done. If the board vendor doesn't mention length matching then it was unlikely to have been done. Most of Digilent's boards with "high-speed" "differential" PMODS mention length matching in the reference manual. Some vendors offer a trace routing report of lengths for certain connectors. If differential signal traces are routed as true differential pairs then using them as single-ended signals might be problematic from a cross-coupling standpoint, especially if you don't take this into account. The only 3.3V differential IOSTANDARD supported by Series7 devices is TMDS and this is best done when the termination is as close to the receiver as possible. All of this does not necessarily mean that you can't design around a board's shortcomings to achieve some level of performance using a logic that the board wasn't designed for. This is one reason why all (most???) Series7 devices offer input delay management and in some cases output delay management features.

There are boards from a few vendors with length matched GPIO on connectors are usually designed for high-speed. 2.56x2.56 mm connectors aren't that.

Not many board vendors are going to go to the expense of designing a high performance board that they intend to sell at a cheap price.

Final comment. If you are going to connect an external board or device to your FPGA board connector then you must assume the digital logic designer role required to do so.

[ManserDimor]

On 9/24/2019 at 1:20 PM, vicentiu said:

Some yes, some no... depends on the board and connector/standard (fmc, pmod, mipi, etc).

If you have a specific board and connector in mind we can tell you how matched (or not) they are.

Hi vincentiu

I appreciate your help.

What about the Arty A7, Arty Z7 and Zybo Z7?

Thanks

[vicentiu]

Some yes, some no... depends on the board and connector/standard (fmc, pmod, mipi, etc).

If you have a specific board and connector in mind we can tell you how matched (or not) they are.