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Victor

Critical warnings in the HDMI Demo Project

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Hello all
 
I tried to implement zybo-z7-hdmi-demo using instructions in the:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start
https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start
and I got 5 critical warnings after Implementation of the this project for Zibo Z7-10 within Vivado 2016.4:

ImplementationDesign Initialization[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_vid_in_axi4s_0_0/system_v_vid_in_axi4s_0_0_clocks.xdc":11]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":5]
[Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":6]
[Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/src/bd/system/ip/system_v_tc_0_0/system_v_tc_0_0_clocks.xdc":6]
Route Design[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
impl_1launch_sdk -workspace E:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/proj/HDMI.sdk -hwspec E:/VICT/Vivado2016_4/Zybo-Z7-10-HDMI/proj/HDMI.sdk/system_wrapper.hdf
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.


Also
reference design
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-dma-audio-demo/start
gives 12 critical warnings after Syntesis:
SynthesisOut-of-Context Module Runssystemsystem_d_axi_i2s_audio_0_0_synth_1[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":55]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":56]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":62]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":65]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":55]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":56]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":62]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_32/fifo_32/fifo_32_clocks.xdc":65]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_4/fifo_4/fifo_4_clocks.xdc":55]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_4/fifo_4/fifo_4_clocks.xdc":56]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_4/fifo_4/fifo_4_clocks.xdc":62]
[Common 17-55] 'get_property' expects at least one object. ["e:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/src/bd/system/ip/system_d_axi_i2s_audio_0_0/src/fifo_4/fifo_4/fifo_4_clocks.xdc":65]
 

As I think the reference designs must have all necessary parts to do systhesis and implementation without the critical warnings.

Please help me to resolve this problem.
 
Thank you,
 
Best regards,
Viktor.

Edited by Victor

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6 answers to this question

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Hello, @Victor!

At a first glance, it seems that your warnings are cause by the fact that you have an undeclared or unpinned clock in your design. Don't forget that constraints are case sensitive.

Let me know if you find the error or not, so I can help give you further assistance if needed.

Good luck!

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Hi @Victor,

Yu can ignore these warnings; I ran the 2016.4 HDMI project (generated the bitstream and launched SDK) on the Zybo Z7-10 and can successfully see my desktop extension.

Please let me know if you have any questions about this.

Thanks,
JColvin

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Hello OvidiuD !

Excuse me for the late reply. I have no possible to do it earlier.
Thank you for your answer.

I used reference design as is.

I do not look any clocks in this design except 
    hdmi_in_clk_n : in STD_LOGIC;
    hdmi_in_clk_p : in STD_LOGIC;

Also in the file Zino-Z7-Master.xds I look constraints for these clocks lines:
set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_n }]; 
set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_p }];

I prepared working project with the following steps:
1) cd E:\VICT\Vivado2016_4\Zybo-Z7-10-DMA\proj
2) Manually replace "\" to the "/":
cd E:/VICT/Vivado2016_4/Zybo-Z7-10-DMA/proj
ENTER
source ./create_project.tcl
ENTER

After that I have got the project that can be found here:
https://drive.google.com/file/d/11uIH3UMdcsWlA6xs-krPw7gkuukwuBru/view?usp=sharing

If you have possible please look this project.
May be I did something wrong and got wrong project.

Thank you.

Best regards
Victor.

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Hello JColvin !

Excuse me for the late reply.
Thank you for your answer.

Implementation gives 5 critical warnings  
and also "Timing constraints are not met".
It is not acceptable for reference design.

Project can be found here:
https://drive.google.com/file/d/11uIH3UMdcsWlA6xs-krPw7gkuukwuBru/view?usp=sharing

If you have possible please look this project.
May be I did something wrong and got wrong project.

Thank you.

Best regards
Victor.

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Hi @Victor,

The project will still work despite the message stating the design failed to meet the timing requirements. I re-generated the bitstream for your project (leaving it otherwise as is) and successfully ran it and displayed the demo image on the monitor.

Thanks,
JColvin

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Hi  JColvin
Thank you for your reply.
I like this reference design.

It really output picture despite critical warning and despite failed to meet timing constraints.
Probably timing constraints are not necessary at all.

Best regards.
Victor.

11 hours ago, JColvin said:

Hi @Victor,

The project will still work despite the message stating the design failed to meet the timing requirements. I re-generated the bitstream for your project (leaving it otherwise as is) and successfully ran it and displayed the demo image on the monitor.

Thanks,
JColvin

 

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